At the recent Hot Chips conference, Intel® unveiled Clearwater Forest, its next-generation Xeon® 6 processor with efficiency cores (E-cores). The unveiling was made by Don Soltis, Xeon Processor Architect and Intel Fellow with over four decades of processor design experience and a long-standing contributor to the Xeon roadmap.… Read More


Two Perspectives on Automated Code Generation
In engineering development, automated code generation as a pair programming assistant is high on the list of targets for GenAI applications. For hardware design obvious targets would be to autogenerate custom RTL functions or variants on standard functions, or to complete RTL snippets as an aid to human-driven code generation.… Read More
Intel’s IPU E2200: Redefining Data Center Infrastructure
We are in the midst of one of the most transformative periods for data center infrastructure. The explosion of AI, cloud-scale workloads, and hyperscale networking is forcing rapid innovation not only in compute and storage, but in the very fabric that connects them. At the recent Hot Chips conference, Pat Fleming gave a talk on… Read More
Static Timing Analysis Signoff – A comprehensive and Robust Approach
By Zameer Mohammed
Once a chip is taped out, changes in design are not possible – Silicon is unforgiving, does not allow postproduction modifications. In contrast, software can be updated after release, but chips remain fixed. Static Timing Analysis (STA) signoff serves as a crucial safeguard against silicon failures.
In modern… Read More
Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs
For decades, high-performance CPU design has been dominated by traditional out-of-order (OOO) execution architectures. Giants like Intel, Arm, and AMD have refined this approach into an industry standard—balancing performance and complexity through increasingly sophisticated schedulers, speculation, and runtime … Read More
Orchestrating IC verification: Harmonize complexity for faster time-to-market
By Marko Suominen and Slava Zhuchenya of Siemens Digital Industries Software.
It’s often said that an orchestra without a conductor is just a collection of talented individuals making noise. The conductor’s role is to transform that potential cacophony into a unified, beautiful symphony. The same concept holds… Read More
Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo
At Hot Chips 2025, Philippe Sauter of ETH Zürich presented Basilisk, a project that may redefine what’s possible with open-source hardware. Basilisk is a 34 mm² RISC-V SoC fabricated at IHP Microelectronics on its open-source 130nm BiCMOS process in Germany. Basilisk, named after the Greco-Roman mythical creature known… Read More
CEO Interview with Nir Minerbi of Classiq
Nir Minerbi is a co-founder and the CEO of Classiq. Nir is highly experienced in leading groundbreaking, multi-national technological projects, from idea to deployment. Nir is a Talpiot alumnus and a master’s graduate in physics as well as electrical and electronics engineering (M.Sc.).
Tell us about Classiq.
Classiq… Read More
Podcast EP305: On Overview of imec’s XTCO Program with Dr. Julien Ryckaert
Dan is joined by Dr. Julien Ryckaert who joined imec as a mixed-signal designer in 2000, specializing in RF transceivers, ultra-low power circuit techniques, and analog-to-digital converters. In 2010, he joined imec’s process technology division in charge of design enablement for 3DIC technology. Since 2013, he oversees… Read More
GlobalFoundries 2025 Update GTS25
“GTS25 brings together leaders from across the semiconductor industry to share their insights on the latest technology trends that enable GF to design the essential chips the world relies on to live, work and connect.”
GlobalFoundries (GF), a leading contract semiconductor manufacturer, plays an important… Read More
Intel’s Pearl Harbor Moment