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Podcast EP358: How Custom Silicon Development Allowed Cisco to Fuel New Innovation for Its Customers

Podcast EP358: How Custom Silicon Development Allowed Cisco to Fuel New Innovation for Its Customers
by Daniel Nenni on 07-31-2026 at 2:00 pm
Categories: Semiconductor

Daniel is joined by Nick Kucharewski Senior Vice President and General Manager for Cisco’s silicon development organization. In this role he is responsible for the end-to-end strategy, cross-functional execution, organization alignment, and product roadmap for Silicon One, Cisco’s uniquely scalable and programmable … Read More

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DAC 2026: The Trouble with John Cooley’s Troublemaker Panel

DAC 2026: The Trouble with John Cooley’s Troublemaker Panel
by Mike Gianfagna on 07-31-2026 at 10:00 am
Categories: EDA, Events
1 Comment

DAC 2026 The Trouble with John Cooley’s Troublemaker Panel

For quite a few years, John Cooley has hosted the Troublemaker Panel at DAC. The event consists of a panel of senior executives from the EDA industry. John Cooley asks his readers for “edgy” questions to ask the panelists and on event day, he does just that. Those with complete responses that are backed with real data from real customers… Read More

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The Difference Between CoWoS-S and CoWoS-R

The Difference Between CoWoS-S and CoWoS-R
by Daniel Nenni on 07-31-2026 at 6:00 am
Categories: 3D IC, AI, Semiconductor, TSMC

The Difference Between CoWoS S and CoWoS R

CoWoS-S and CoWoS-R are two versions of TSMC’s Chip-on-Wafer-on-Substrate advanced packaging platform. Both technologies are designed to combine high-performance processors, chiplets and high-bandwidth memory, or HBM, within a single package. This shortens the electrical connections between computing and memory components,… Read More

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From Photonics Precision to Repeatable Evidence

From Photonics Precision to Repeatable Evidence
by Moh Kolb on 07-30-2026 at 2:00 pm
Categories: Photonics

Photroinc probe july112 semi

Why Optical Probing Is Becoming a Manufacturing Boundary for Silicon Photonics

Silicon photonics has already shown that extremely precise optical alignment is possible.

In controlled laboratory environments, engineers can align fibers, waveguides, grating couplers, edge couplers, modulators, detectors, and electrical… Read More

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Industry’s First Certified Automotive Grade PUF for Software Defined Vehicles

Industry’s First Certified Automotive Grade PUF for Software Defined Vehicles
by Kalar Rajendiran on 07-30-2026 at 10:00 am
Categories: AI, Automotive, EDA, IP, Security, Synopsys

Automotive PUF Premium System Level Diagram

Software defined vehicles (SDVs) are transforming the automotive industry. Today’s vehicles are connected computing platforms that rely on advanced processors, artificial intelligence (AI), over the air (OTA) software updates, cloud services, and vehicle to everything (V2X) communications. Every electronic … Read More

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Formal Acceleration on FPGA. Innovation in Verification

Formal Acceleration on FPGA. Innovation in Verification
by Bernard Murphy on 07-30-2026 at 6:00 am
Categories: Cadence, EDA

Innovation New

Extending hardware acceleration to formal verification is a powerful idea to extend hardware acceleration to a verification domain that has not got much attention for acceleration. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More

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Previewing FMS 2026: The Next Frontier of Enterprise Memory, CXL, and AI-Era Storage

Previewing FMS 2026: The Next Frontier of Enterprise Memory, CXL, and AI-Era Storage
by Daniel Nenni on 07-29-2026 at 10:00 am
Categories: Events, Semiconductor
2 Comments

FMS 2026 Partner socials (5) (1)

For anyone tracking enterprise infrastructure, the storage landscape is moving at a breakneck pace. The explosive growth of generative AI, multi-million token context windows, and massive data-centric workloads have pushed traditional memory and storage architectures to their absolute limits.

This August, the industry… Read More

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ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation

ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation
by Daniel Nenni on 07-29-2026 at 6:00 am
Categories: EDA, Prototyping, S2C EDA

S2C FPGA Prototyping

For ASIC design teams, the gap between RTL simulation and first silicon remains one of the most consequential stages of the development cycle. Simulation provides controllability and visibility, but it cannot always reproduce the software workloads, interface behavior, clock interactions, and sustained system activity… Read More

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Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas

Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas
by Daniel Nenni on 07-28-2026 at 2:00 pm
Categories: CEO Interviews

Simon Davidmann

Simon Davidmann is a renowned EDA industry pioneer and serial technology entrepreneur with more than 40 years of experience in simulation and verification. After Synopsys acquired Imperas, which he founded in 2005, he was Synopsys Vice President responsible for Processor Modeling and Simulation. He left Synopsys in 2025 and… Read More

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Quadric Extends Series C to $46 Million as Edge AI Demand Accelerates

Quadric Extends Series C to $46 Million as Edge AI Demand Accelerates
by Daniel Nenni on 07-28-2026 at 10:00 am
Categories: IP, Quadric

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Quadric has extended its Series C financing to $46 million through a second close led by the International Finance Corporation, the private-sector investment arm of the World Bank Group. The transaction raises Quadric’s total capital secured to approximately $90 million and strengthens its ability to commercialize programmable… Read More