Chuck McClish is the founder of Lattrex Inc., a fabless semiconductor startup building Kyttar, an asynchronous, clockless reconfigurable processor for real-time signal processing. He spent 15 years at Microchip Technology in chip design and verification, working across RTL design, UVM verification, synthesis, place-and-route,… Read More
Industry's First Certified Automotive Grade PUF for Software Defined VehiclesSoftware defined vehicles (SDVs) are transforming the automotive…Read More
Formal Acceleration on FPGA. Innovation in VerificationExtending hardware acceleration to formal verification is a…Read More
Previewing FMS 2026: The Next Frontier of Enterprise Memory, CXL, and AI-Era StorageFor anyone tracking enterprise infrastructure, the storage landscape…Read More
ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware ValidationFor ASIC design teams, the gap between RTL…Read More
Security by Design: Arteris Expands Its Partnership with ArmArteris has expanded its partnership with Arm to…Read MorePodcast EP358: How Custom Silicon Development Allowed Cisco to Fuel New Innovation for Its Customers
Daniel is joined by Nick Kucharewski Senior Vice President and General Manager for Cisco’s silicon development organization. In this role he is responsible for the end-to-end strategy, cross-functional execution, organization alignment, and product roadmap for Silicon One, Cisco’s uniquely scalable and programmable … Read More
DAC 2026: The Trouble with John Cooley’s Troublemaker Panel
For quite a few years, John Cooley has hosted the Troublemaker Panel at DAC. The event consists of a panel of senior executives from the EDA industry. John Cooley asks his readers for “edgy” questions to ask the panelists and on event day, he does just that. Those with complete responses that are backed with real data from real customers… Read More
The Difference Between TSMC CoWoS-S and CoWoS-R
CoWoS-S and CoWoS-R are two versions of TSMC’s Chip-on-Wafer-on-Substrate advanced packaging platform. Both technologies are designed to combine high-performance processors, chiplets and high-bandwidth memory, or HBM, within a single package. This shortens the electrical connections between computing and memory components,… Read More
From Photonics Precision to Repeatable Evidence
Why Optical Probing Is Becoming a Manufacturing Boundary for Silicon Photonics
Silicon photonics has already shown that extremely precise optical alignment is possible.
In controlled laboratory environments, engineers can align fibers, waveguides, grating couplers, edge couplers, modulators, detectors, and electrical… Read More
Industry’s First Certified Automotive Grade PUF for Software Defined Vehicles
Software defined vehicles (SDVs) are transforming the automotive industry. Today’s vehicles are connected computing platforms that rely on advanced processors, artificial intelligence (AI), over the air (OTA) software updates, cloud services, and vehicle to everything (V2X) communications. Every electronic … Read More
Formal Acceleration on FPGA. Innovation in Verification
Extending hardware acceleration to formal verification is a powerful idea to extend hardware acceleration to a verification domain that has not got much attention for acceleration. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,… Read More
Previewing FMS 2026: The Next Frontier of Enterprise Memory, CXL, and AI-Era Storage
For anyone tracking enterprise infrastructure, the storage landscape is moving at a breakneck pace. The explosive growth of generative AI, multi-million token context windows, and massive data-centric workloads have pushed traditional memory and storage architectures to their absolute limits.
This August, the industry… Read More
ASIC-to-FPGA Turnkey Prototyping Bundle: A Practical Path to Earlier Hardware Validation
For ASIC design teams, the gap between RTL simulation and first silicon remains one of the most consequential stages of the development cycle. Simulation provides controllability and visibility, but it cannot always reproduce the software workloads, interface behavior, clock interactions, and sustained system activity… Read More
Interview with Simon Davidmann, AI + EDA Researcher and Former CEO of Imperas
Simon Davidmann is a renowned EDA industry pioneer and serial technology entrepreneur with more than 40 years of experience in simulation and verification. After Synopsys acquired Imperas, which he founded in 2005, he was Synopsys Vice President responsible for Processor Modeling and Simulation. He left Synopsys in 2025 and… Read More


ASML High-NA EUV is Not Ready for High-Volume Production