CEO Interview with Charlie Cheng of CEO of TeRAM

Charlie Cheng is CEO of TeRAM, with four decades of technology experience focused on microprocessor architecture and semiconductor memory. Before TeRAM, he worked on several AI processors, including multiple generations of Meta’s MTIA accelerators beginning in 2019. Previously, he served as CEO of Kilopass, a semiconductor memory IP company, where he secured SK hynix and Samsung as licensees before the company’s acquisition by Synopsys. His experience at Kilopass gave him firsthand insight into the memory industry and the opportunities that inspired him to start TeRAM. Charlie began his career as a systems engineer at IBM.

Tell us about your company?

TeRAM builds custom 3D SRAM memory chips for frontier AI use. We spun out of Kilopass in 2018 after the Synopsys acquisition and raised our Seed rounds in 2026. The company is privately held, and based in the heart of the Silicon Valley, with development centers & fabrication partner in Asia. We’ve raised $36.5M so far to validate our technology.

What problems are you solving?

In short, we believe we can breakdown the Memory Wall and continue the scaling & adoption of frontier AI models. Since the rollout of ChapGPT 3.5, AI models have increased 10X in size and together with agentic workloads have stressed the memory subsystem to make AI both expensive and power hungry.  We believe TeRAM holds the key to eliminate the Memory Wall.

What application areas are your strongest?

We believe we are strong in all phases of AI development & deployment. We can scale in capacity for frontier model training, and scale in bandwidth for decode portion of the inference. Further, we believe with our unique packaging advantages, we can extend beyond the current datacenter need for lower power, higher bandwidth, and into on-premise AI deployments, and perhaps all the way to the smallest edge devices such as AR/VR.

What keeps your customers up at night?

The memory wall — compute has scaled faster than memory can keep up, on both bandwidth and density. Existing memory technologies each hit real physical limits as they’re pushed harder, and those limits are becoming a genuine bottleneck for AI.

What does the competitive landscape look like and how do you differentiate?

Existing DRAM and SRAM companies are all working diligently to address this Memory Wall, that’s for sure.  However, we feel we have a completely unique approach to the problem, specifically how it results in a easier & more efficient packaging to deliver higher capacity, bandwidth at lower power consumption.

What new features/technology are you working on?

While we are not at this time disclosing too much about the technologies, I think it’s important to note that much is needed to extend the current DRAM and HBM roadmap to integrate with hybrid-bonding while waiting for the true 3D DRAM bit-cell mass production.  So there is a window of opportunity for a new way of solving the Memory Wall problem.

How do customers normally engage with your company?

As mentioned, our business model is to sell memory chips customized for each compute chip.  So we are somewhat similar to Broadcom’s ASIC business. Customers such as hyperscalars or semiconductor companies provide us with specifications and we develop customized chips for their compute chips.

Contact TeRAM

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