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The Linley Group is well-known for their esteemed Microprocessor Report publication, now in its 28th year. Accompanying their repertoire of industry reports, TLG also sponsors regular conferences, highlighting the latest developments in processor architecture and implementation.
One of the highlights of the conference… Read More
XM4 DSP has been enriched with CEVA Deep Neural Network (CDNN) Software Framework. Some explanation could be useful before jumping into CDNN. The “Deep” of CDNN comes from “Deep Learning”, a family of neural network methods using high number of layers, so a deep network. The most popular deep learning neural network method is the… Read More
Wi-Fi is the unsung hero of the mobile revolution. Some people even call it the real Internet. In retrospect, smartphones took off partly because Apple forced mobile operators to seriously consider handsets with Wi-Fi capabilities. Now Wi-Fi is an intrinsic networking component serving smartphones, tablets and notebook computers… Read More
I suppose you might have something better to do next Wednesday but, seriously, it had better be pretty good. I admit I’m biased (I was the Atrenta CTO until very recently) but even given that and mixing metaphors, Atrenta really knocked it out of the park when they got the 49er stadium for their User Group meetings. You don’t have to … Read More
As the semiconductor consolidation continues and thousands of semiconductor professionals update their LinkedIn profiles, the march to create new silicon opportunities is increasing at a rapid pace. It is 1980s deja vu all over again when the fabless business model reenergized the semiconductor industry and brought affordable… Read More
You may not know Tensilica DSP IP core, but you probably use Tensilica DSP powered systems in your day to day life. Every year, over 2 billion DSP cores equip IC in thousands of designs supporting IoT, Mobile Phones, Storage/SSD, Networking, Video, Security, Cameras… and more. Why DSP processing, the foundation of all Tensilica… Read More
To describe the latest methodology for the addition of Design for Manufacturability fill shapes to design layout data, it’s appropriate to borrow a song title from Bob Dylan – The Times They Are A Changin’. The new technical requirements are best summarized as: “The goal is now to add as much fill as possible, which (ideally) looks… Read More
(I changed the title of this piece as an experiment) Paul McLellan recently wrote on the topic of new ventures crossing the chasm (getting from initial but bounded success to a proven scalable business). That got me to thinking about the EDA market in general. In some ways it has a similar problem, stuck at $5B or so and single-digit… Read More
Most of the discussion around Xilinx UltraScale parts in FPGA-based prototyping modules has been on capacity, and that is certainly a key part of the story. Another use case is developing, one that may be even more important than simply packing a bigger design into a single part without partitioning. The real win with this technology… Read More
It used to be that if you went to a processor conference, you could expect to spend hours listening to talks about pipelining, cache schemes and processor architecture. Well, I went to the Linley Processor Conference this week in Santa Clara and found the topics pretty compelling. Processors are in just about everything. It is easier… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival