The majority of my 40+ year career has been spent managing the relationship between leading-edge semiconductor design and manufacture, working with just about every commercial foundry and top customer in one way or another. It’s my thing—it fascinates me. I’m also a fan of disruption, and the latest disruptions the semiconductor… Read More
The Evolution of RISC-V and the Role of Andes Technology in Building a Global EcosystemDuring my frequent trips to Taiwan as a…Read More
Capability Hardware Enhanced RISC Instructions CHERI AllianceThe CHERI Alliance is a non-profit organization dedicated…Read More
Operationalizing Secure Semiconductor Collaboration: Safely, Globally, and at ScaleSemiconductor manufacturing is among the most complex industrial…Read More
Keynote: On-Package Chiplet Innovations with UCIeIn the rapidly evolving landscape of semiconductor technology,…Read MorePodcast EP335: The Far Reaching Impact of UCIe with Dr. Debendra Das Sharma
Daniel is joined by Dr. Debendra Das Sharma, a Senior Fellow and Chief I/O architect in the Data Platforms and Artificial Intelligence Group at Intel. He is a member of the National Academy of Engineering (NAE), Fellow of IEEE, and Fellow of International Academy of AI Sciences. He is a leading expert on I/O subsystem and interface… Read More
Agentic AI and the Future of Engineering
Agentic AI emerges in this Synopsys Converge keynote not as a futuristic add-on, but as a practical response to the growing complexity of engineering. In the speaker’s view, the traditional way of designing chips, systems, and intelligent products is no longer sufficient for the era of physical AI. Engineers are now dealing with… Read More
WEBINAR: Outrunning the Data Wave – Why we need to keep pace with the coming 400% data surge
The semiconductor manufacturing industry has hit a new era of data intensity. We know that we need to look at alternatives to silicon and that electrical interconnects are unable to keep pace. We know we need to design more chiplets and alter microchip architecture. But how much data are we talking specifically, and how much
Ravi Subramanian on Trends that are Shaping AI at Synopsys
Right before the Synopsys Converge Keynote I caught an interview with Ravi Subramanian, Chief Product Management Officer at Synopsys, which highlights several important trends shaping the future of AI, semiconductor technology, and engineering. His discussion focuses on how the worlds of silicon design and system engineering… Read More
Axiomise Introduces nocProve to Transform NoC Design Verification
Axiomise has recently launched a new verification tool called nocProve which will transform how Network-on-Chip designs are validated in modern hardware development, absolutely.
The tool is designed to be the first configurable formal verification application specifically created for NoC implementations. It addresses… Read More
Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit
The Chiplet Summit recently concluded. Multi-die heterogeneous design is a hot topic these days and chiplets are a key enabler for this trend. The conference was noticeably larger this year. There were many presentations and exhibits that focused on areas such as how to design chiplets, what standards are important, how to integrate… Read More
Intel Foundry: How They Got Here and Scenarios for Improvement
How do you get a shortage while not growing???
Intel Announced earnings in January. Then David Zinsner presented updates on business this week. David is open when talking and always shares 2-3 things he probably should not share. Often he shares things some of us know, but we cannot present because it is not public. Then he makes it… Read More
The Next Hurdle AI Systems Must Clear
AI isn’t having an easy ride. The media and Wall Street swing wildly between extremes on any hint of a shift in AI sentiment. Dickens saw this coming: “It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, it was the epoch of belief, it was the epoch of incredulity, it was the season of … Read More
Why Your LLM-Generated Testbench Compiles But Doesn’t Verify: The Verification Gap Problem
By Vikash Kumar, Senior Verification Architect | Arm | IEEE Senior Member.
The Problem Every Verification Engineer Recognizes
You ask an LLM to generate a UVM testbench. It produces 25 files. Everything compiles. You run the simulation — and nothing happens. The scoreboard reports zero checks. The slave driver stops after 10… Read More


Things From Intel 10K That Make You Go …. Hmmmm