Instance

Array
(
    [title] => Recent Forum Threads
    [title_url] => 
    [ignore_sticky] => 0
    [exclude_current] => 0
    [limit] => 10
    [sluglist] => ["jobs-dashboard"]
    [rw_opt] => Array
        (
            [widget_select] => 1
            [pageid_281769] => 1
            [pageid_281772] => 1
        )

    [display_widget_mobile] => 
    [rw_opt_exclude] => Array
        (
            [pageid_274493] => 1
            [cpt_podcast] => 1
            [cpta_podcast] => 1
            [category_16613] => 1
            [category_16631] => 1
            [taxonomy_series] => 1
            [pageid_354254] => 1
        )

    [node_id] => Array
        (
            [0] => 2
        )

)

Threads

The Accidental Infrastructure: How Crypto Miners Built the Foundation of the AI BoomMost crypto forty-niners died broke in a warehouse…Read More

From Detection to Safety: Reframing Fault Simulation for Functional SafetyIn the early 1980s, when computer-aided engineering (CAE),…Read More

Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative MattersThe future of work will not be shaped…Read More

Foundation IP for Intel 18A: Technical Overview and Why It MattersSynopsys Foundation IP for Intel 18A is a…Read More

WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA toolsThe real promise of AI in EDA is…Read More

‹›

Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena

Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena
by Daniel Nenni on 07-10-2026 at 2:00 pm
Categories: Uncategorized

Daniel is joined by Sagar Saxena, Senior Product Engineer at Siemens EDA specializing in computational lithography, optical proximity correction (OPC), and advanced patterning solutions for leading-edge semiconductor manufacturing. Sagar has led the development and deployment of advanced OPC technologies, including… Read More

July 10, 2026July 10, 2026

CEO Interview with Mark Ren of Agentrys

CEO Interview with Mark Ren of Agentrys
by Daniel Nenni on 07-10-2026 at 10:00 am
Categories: Agentrys, CEO Interviews, EDA

Mark Ren has 26 years of EDA and AI R&D experience spanning IBM Research and NVIDIA Research, driving design automation innovations that power modern chip design. He received the IBM Corporate Award for contributions to the design closure for high-performance microprocessors. At NVIDIA, he helped establish the company

July 10, 2026July 9, 2026

TSMC A16 Backside Power at VLSI 2026

TSMC A16 Backside Power at VLSI 2026
by Daniel Nenni on 07-10-2026 at 6:00 am
Categories: 3D IC, Semiconductor, TSMC

TSMC’s A16 technology, presented as Paper T1.5 at the June 2026 IEEE/JSAP VLSI Symposium, marks the company’s first angstrom-class CMOS platform combining enhanced nanosheet gate-all-around transistors with backside power delivery. The key integration feature is Super Power Rail, or SPR, which TSMC describes as a backside… Read More

July 9, 2026July 9, 2026

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
by Kalar Rajendiran on 07-09-2026 at 2:00 pm
Categories: AI, Chiplet, IP

The semiconductor landscape is currently undergoing a structural transformation as the “Data-Centric Shift” moves the industry’s center of gravity from smartphones toward High-Performance Computing (HPC) and AI infrastructure.

This transition is clearly validated by TSMC’s 2025 filings, which show… Read More

July 9, 2026July 9, 2026

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise
by Daniel Nenni on 07-09-2026 at 10:00 am
Categories: EDA, Semiconductor Services

Electronic Design Automation, or EDA, is the software infrastructure that transforms a hardware specification into a manufacturable integrated circuit. At advanced process nodes, the problem is no longer simply drawing transistors or connecting gates. A modern system-on-chip contains billions of standard cells, hundreds… Read More

July 9, 2026July 9, 2026

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA
by ChandraM on 07-09-2026 at 6:00 am
Categories: AI, EDA

Over the last year, the EDA industry has started using a new vocabulary: agents, super agents, mental models, native skills, playbooks, RAG, MCP, autonomous workflows, and AI-first design.

The language is new, but the motivation is familiar to anyone who has worked in chip design.

Design complexity keeps increasing. The number… Read More

July 8, 2026July 9, 2026

MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative

MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative
by Daniel Nenni on 07-08-2026 at 2:00 pm
Categories: EDA, Events, Moores Lab (AI)

For decades, semiconductor innovation has been constrained not by imagination, but by engineering capacity. While transistor density has continued to advance, the process of building chips has remained fundamentally manual, fragmented across specifications, RTL, verification, debugging, coverage analysis, and signoff.… Read More

July 8, 2026July 8, 2026

Caspia Technologies is pioneering a new, agentic chip and system security approach at DAC 2026

Caspia Technologies is pioneering a new, agentic chip and system security approach at DAC 2026
by Daniel Nenni on 07-08-2026 at 10:00 am
Categories: Caspia Technologies, Events, Security

Caspia’s advanced tools and agents blend seamlessly with existing design flows to add expert-level security verification capabilities for all design teams. Founded in 2020 and headquartered in Gainesville, Florida, Caspia brings together expertise in chip design, fabrication, test, and verification with a deep understanding… Read More

July 8, 2026July 3, 2026

IP Lifecycle Management in the AI Era

IP Lifecycle Management in the AI Era
by Bernard Murphy on 07-08-2026 at 6:00 am
Categories: AI, EDA, Perforce

designer trying to find best IP options in a tangle of choices

Large design enterprises have multiple concurrent activities around IP of various types: software/firmware, blocks defined in RTL or HLS, verification IPs of multiple different types, physical implementations, scripts/files for timing, power management, etc., etc. Each of these continues to evolve and branch to serve … Read More

July 7, 2026July 9, 2026

See Autonomous Chip Design in Action with ChipAgents at DAC 2026

See Autonomous Chip Design in Action with ChipAgents at DAC 2026
by Daniel Nenni on 07-07-2026 at 2:00 pm
Categories: ChipAgents AI, EDA

Making the AI wave at DAC 2026 in Long Beach

DAC comes to Long Beach for the first time in 2026, with artificial intelligence expected to be one of the central topics across the conference program and exhibition floor.

For semiconductor design and verification teams, the discussion has moved beyond whether AI can assist engineers.… Read More

The Packaging PDK Is the Missing Layer for Co-Packaged Optics
Thank you to Daniel Nenni and SemiWiki for publishing my latest article: The Packaging PDK Is the Missing Layer for…

— moh.kolb on July 8, 2026
The Packaging PDK Is the Missing Layer for Co-Packaged Optics
Very interesting. Thanks.

— U235 on July 8, 2026
Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031
N+3 is denser than N6: https://newsletter.semianalysis.com/p/steel-smic-n3-teardown?open=false

— Fred Chen on July 5, 2026
Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031
Fixed, thank you.

— Daniel Nenni on July 4, 2026
Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031
The article is not correct. EUV equipment is not primarily produced by ASML. It is only produced by ASML. It…

— AndyG on July 4, 2026
Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?
Nice writeup

— Rahul Razdan on June 27, 2026
Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs
In a DoD centric III-V fab I had wafers run in a few decades ago, yield was miserable, but adequate…

— PBealo on June 27, 2026
Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs
Another thing that can help improve availability is a very old but often overlooked basic bedrock: Having good SPC, that…

— benb on June 24, 2026

Webinar: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools

Webinar: Scaling Compute Connectivity with PCIe and CXL: Chip-to-Chip and Emerging Architectures

Advanced Packaging Summit 2026

Webinar: Formal Verification for Non-Specialists

10th Edition — IEEE International Test Conference INDIA 2026

Podcast EP354: How Siemens EDA is Conquering New Lithography Challenges with Sagar Saxena

CEO Interview with Mark Ren of Agentrys

TSMC A16 Backside Power at VLSI 2026

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

SemiAnalysis EDA Market Primer – Market Dynamics, Cadence, Synopsys, Siemens, China EDA Rise

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA

MooresLabAI at DAC 2026: Why the Future of Semiconductor Engineering Is Agentic, Not Just Generative

Caspia Technologies is pioneering a new, agentic chip and system security approach at DAC 2026

IP Lifecycle Management in the AI Era

See Autonomous Chip Design in Action with ChipAgents at DAC 2026

Recent Forum Threads

Japan’s Rapidus Takes on TSMC With Aggressive 2nm Pricing

Apple Sues OpenAI for Stealing Trade Secrets, Latter’s IPO Valuation Logic to Face Clear Pressure

Why CPUs Are Now at the Center of the AI Race

U.S.-backed chip startup xLight aims to raise $350 million for an EUV alternative

Apple to spend $30 billion on Broadcom chips as it boosts US sourcing

TSMC's Moat Revealed: 93,000 Certified IPs Build a Hundred-Billion-Dollar Ecosystem Barrier

Thermal Management Challenges in Chiplet-based Architectures

Taiwanese chipmaker Nanya plans $6 billion in spending in 2027, riding AI boom

Samsung chip division's single-year profits beat its past 40 years of profits, combined.

How TSMC Helped SK Hynix Overtake Samsung in the AI Memory Race

Recent Article Comments

The Packaging PDK Is the Missing Layer for Co-Packaged Optics

The Packaging PDK Is the Missing Layer for Co-Packaged Optics

Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031

Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031

Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031

Intel 18A vs Intel 18A-P: What Is the Difference and Why Does It Matter?

Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs

Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs