Just prior to the opening of the 54[SUP]th[/SUP] Design Automation Conference, Mentor, a Siemens company, and PhoeniX Software issued a press release announcing a new integration between their tools to help designers of photonic ICs (PICs) to close the loop for manufacturing sign-off verification. This is a significant piece… Read More
Captain America: Can Elon Musk Save America's Chip Manufacturing Industry?Intel has posted three consecutive years of falling…Read More
WEBINAR: Reclaiming Clock Margin at 3nm and BelowAt 3nm and below, clock networks have quietly…Read More
WEBINAR: HBM4E Advances Bandwidth Performance for AI TrainingThe rapid proliferation of LLMs and other AI…Read More
Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design EnablementThe recent Chiplet Summit in Santa Clara was…Read More
Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB DesignThough terminology sometimes get fuzzy, consensus holds that…Read MoreCadence Explores Smarter Verification
Verification as an effectively unbounded problem will always stir debate on ways to improve. A natural response is to put heavy emphasis on making existing methods faster and more seamless. That’s certainly part of continuous improvement but sometimes we also need to step back and ask the bigger questions – what is sufficient … Read More
Exclusive – GLOBALFOUNDRIES discloses 7nm process detail
In a SemiWiki EXCLUSIVE – GLOBALFOUNDRIES has now disclosed the key metrics for their 7nm process. As I previously discussed in my 14nm, 16nm, 10nm and 7nm – What we know now blog GLOBALFOUNDRIES licensed their 14nm process from Samsung and decided to skip 10nm because they thought it would be a short-lived node. At … Read More
Embedded FPGA’s create new IP category
FPGA’s are the new superstar in the world of Machine Learning and Cloud Computing, and with new methods of implementing them in SOC’s there will be even more growth ahead. FPGA’s started out as a cost effective method for implementing logic without having to spin an ASIC or gate array. With the advent of the web and high performance… Read More
LETI Days 2017: FD-SOI, Sensors and Power to Sustain Auto and IoT
I have attended last week to the LETI Days in Grenoble, lasting two days to mark the 50[SUP]th[/SUP] anniversary of the CEA subsidiary. Attending to the LETI Days is always a rich experience: LETI is a research center counting about 3000 research engineers, but LETI is also a start-up nursery. The presentations are ranging from … Read More
Webinar: Synopsys on Clock Gating Verification with VC Formal
Clock gating is arguably the mostly widely-used design method to reduce power since it is broadly applicable even when more sophisticated methods like power islands are ruled out. But this style can be fraught with hazards even for careful designers. When you start with a proven-correct logic design and add clock gating, the logic… Read More
Open Source Hardware: Chiplicity.io
What’s new with eFabless? Let’s check in with CEO Michael Wishart (MSW) and CTO Mohamed Kassem CTO (MKK):… Read More
ADAS and Vision from Cadence
A huge theme at #54DAC this year was all things automotive and in particular the phrase ADAS (Assisted Driver Assistance Systems), so I followed up with Raja Tabet a corporate VP of emerging technology at Cadence. We met on Monday in a press room where I quickly learned that Cadence has been serving the automotive industry for the … Read More
Nvidia Handles Data, Senate with Care
When speaking before the U.S. Senate or Congress one has to choose one’s words carefully. The temptation, when one is speaking before legislators and microphones and cameras, is to tell it like it is and speak truth to power. The reality is that the power of the legislators and the microphones and the cameras must be respected and,… Read More
HW and SW Co-verification for Xilinx Zynq SoC FPGAs
It constantly amazes me at how much FGPA companies like Xilinx have done to bring ARM-based CPUs into a programmable SoC along with FPGA glue logic. Xilinx offers the Zynq 7000 and Zynq UltraScale+ SoCs to systems designers as a way to quickly get their ideas into the marketplace. A side effect of all this programability and flexibility… Read More


Chemical Origins of Environmental Modifications to MOR Lithographic Chemistry