RISC-V and AI: The Architecture Shift Is NowThe semiconductor industry has experienced several defining transitions…Read More
PowerArtist RTL Power Estimation Folds into KeysightBack in the late 1990s, Sente launched a…Read More
Intel Foundry Expands the 18A Platform with 18A-P and Demonstrates Long-Term Technology Leadership at VLSI 2026At the 2026 VLSI Symposium, Intel Foundry provided…Read More
GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneckAs semiconductor manufacturing pushes toward advanced nodes with…Read More
A tower-like heterogeneous packaging architecture for the AI era VEMC: The Vertical System…Read More
I wrote last month about CEVA’s Dragonfly-NB1 platform, a single-chip IoT solution supporting narrow-band cellular communication; this can meet aggressive total solution price-targets for high-volume deployment, long-range access and the low-power needed for 10+ year battery lifetimes. That solution, based on Release… Read More
The IEEE Interconnect Technology Conference (IITC): Advanced Metallization Conference was held June 4th through 7th in Santa Clara. Imec presented multiple papers on comparing copper, cobalt and ruthenium interconnect. One paper in particular caught my eye: Marleen H. van der Veen, # N. Heylen, O. Varela Pedreira, S. Decoster,… Read More
This was my 35th DAC and it did not disappoint, especially when it came to the DAC Drama Department. This year DAC proved once again that it is THE place for semiconductor professionals and academics to learn and network. The big news is that Synopsys did not reserve a booth for 56DAC in Las Vegas next year which resulted in quite a bit… Read More
In the 1930s, psychologist B.F. Skinner put rats in boxes and taught them to push levers to receive a food pellet. The pushed the levers only when hungry, though. To get the rats to press the lever repeatedly, even when they did not need food, he gave them a pellet only some of the time, a concept now known as intermittent variable rewards.… Read More
I joined Texas Instruments (TI) in 1972. Most Stanford PhD’s in my field at that time remained in the Bay Area to work for Fairchild, National Semiconductor, HP or other local companies. But TI was the largest semiconductor company and there were plenty… Read More
As we have been warning for months the China trade issue continues to grow and accelerate. As we are approaching the June 30th cliff (when export sanctions will be announced) it seems as if the administration has given the industry a kick so we fly even further. The US will also restrict Chinese investment in US tech companies. The … Read More
The second keynote at Mentor’s U2U this year was given by Hooman Moshar, VP of Engineering at Broadcom, on the always (these days) important topic of design for power. This is one of my favorite areas. I have, I think, a decent theoretical background in the topic, but I definitely need a periodic refresh on the ground reality from the… Read More
At the Imec technology forum in Belgium, Dan Mocuta and Juliana Radu presented “Evolution and Disruption: A Perspective on Logic Scaling and Beyond”, I also had a chance to sit down with Dan and discuss the presentation.
Device scaling
Scaling of devices will only get you so far, you need to look at new devices and new… Read More
If integrating an embedded FPGA (eFPGA) into your ASIC or SoC design strikes you as odd, it shouldn’t. ICs have been absorbing almost every component on a circuit board for decades, starting with transistors, resistors, and capacitors — then progressing to gates, ALUs, microprocessors, and memories. FPGAs are simply one more… Read More
The second Bay Area RISC-V Meetup event was held at the DoubleTree Hilton in Burlingame on June 19 with about 150 attendees. This event was hosted by SiFive and started with a networking session. The topics and speakers for the evening were:
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Available Is Not In Control: Balancing Output, Quality, and Risk in High-Volume Fabs