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If you are currently in the design phase of a GaN-based T/R module for an AESA radar or LEO Satcom program, there is a supply chain dynamic unfolding right now that deserves more attention than it is getting in the RF design community: the foundry capacity picture for GaN-on-SiC in 2026 has become significantly more complicated than it was eighteen months ago, and the reasons behind it are structural rather than cyclical.
The conventional assumption in RF design has been that GaN-on-SiC foundry capacity is primarily a radar and defense story — WIN Semiconductors, Wolfspeed, UMS, and a handful of others serving a stable set of defense prime integrators with predictable multi-year program volumes. That assumption is no longer accurate.
In February 2026, as conflict in the Middle East prioritized electronic warfare and anti-drone defense, the US Department of Defense invoked emergency procurement powers and legally mandated that top-tier domestic semiconductor foundries prioritize military GaN orders over commercial 5G and consumer electronics applications. This created an immediate and measurable tightening of available foundry slots for commercial and dual-use radar programs that do not fall under the prioritized DoD contracts — precisely the programs that many non-US integrators and fabless RF IP companies depend on.
Simultaneously, a second demand stream has emerged that was not fully anticipated: the pivot toward GaN-on-SiC for AI infrastructure. NVIDIA is reportedly planning to replace traditional silicon interposers with silicon carbide in its next-generation Rubin architecture, targeting higher performance — a development that could redirect meaningful SiC substrate capacity toward data center applications, compressing availability for RF device manufacturers who share the same upstream substrate supply chain.
On the downward pressure side: rapid expansion of SiC capacity from Chinese players has led to significant price erosion — approximately a 30% drop in SiC wafer prices in 2024. Chinese entrants such as Tankeblue and Guangdong TySiC have grown rapidly by leveraging subsidized utilities and offering 6-inch wafers at USD 400–500, forcing incumbents to differentiate on defect density and technical support rather than price.
On the upward pressure side: high wafer costs, often USD 1,000 to USD 2,000 per unit, continue to slow adoption among cost-sensitive manufacturers for premium-tier substrates from Western suppliers — and the DoD prioritization mandate described above means that the remaining non-reserved foundry capacity at US and allied fabs is being priced at a premium. For a design team buying production-qualified GaN-on-SiC from a Tier-1 Western foundry without a long-term supply agreement already in place, the effective cost per wafer slot has increased, not decreased.
The bifurcation matters for T/R module designers: the low-cost Chinese substrates are not yet qualified for most defense radar applications, and yield rates for GaN and SiC materials remain lower than traditional silicon, impacting overall profitability — particularly at smaller volumes where a yield drop of 5–10% on an already expensive wafer run is a material cost event.
For a radar program with a tape-out window in the next 12–18 months, this gap is not theoretical. It is a scheduling and budgeting reality.
First, if your T/R module design depends on a specific GaN-on-SiC process node at a Western foundry — WIN Semiconductors' 250nm or 120nm processes, for instance — and you do not have a capacity reservation or multi-year supply agreement in place, the time to initiate that conversation is now, not at the pre-production stage. The foundries with the most relevant processes for radar FEM and HPA applications are operating closer to capacity utilization than their public communications suggest.
Second, the cost delta between a design using a Western-foundry qualified process (likely required for defense export compliance) and a Chinese-foundry alternative is narrowing on paper but widening in practice for programs that have specific substrate provenance requirements. Building that constraint into your BOM cost model early avoids unpleasant re-sourcing conversations late in the program.
Third, for teams evaluating whether to license production-ready GaN IP versus develop in-house: the foundry access problem does not disappear with in-house design capability. An IP block that comes with existing foundry tape-out data, characterized silicon, and an established production relationship with the process owner reduces the foundry slot negotiation from a zero-baseline conversation to a capacity expansion discussion — a meaningfully different starting position.
If you are working on a T/R module program with a tape-out window in the next 12–18 months and want to see actual characterization data rather than simulated specs, the full IP catalogue is available on Design & Reuse. — including S-parameter models and integration documentation for each part number. For teams further along in evaluation, VSI's engineering team is available for direct technical discussion.
Two demand streams, one constrained substrate
The conventional assumption in RF design has been that GaN-on-SiC foundry capacity is primarily a radar and defense story — WIN Semiconductors, Wolfspeed, UMS, and a handful of others serving a stable set of defense prime integrators with predictable multi-year program volumes. That assumption is no longer accurate.
In February 2026, as conflict in the Middle East prioritized electronic warfare and anti-drone defense, the US Department of Defense invoked emergency procurement powers and legally mandated that top-tier domestic semiconductor foundries prioritize military GaN orders over commercial 5G and consumer electronics applications. This created an immediate and measurable tightening of available foundry slots for commercial and dual-use radar programs that do not fall under the prioritized DoD contracts — precisely the programs that many non-US integrators and fabless RF IP companies depend on.
Simultaneously, a second demand stream has emerged that was not fully anticipated: the pivot toward GaN-on-SiC for AI infrastructure. NVIDIA is reportedly planning to replace traditional silicon interposers with silicon carbide in its next-generation Rubin architecture, targeting higher performance — a development that could redirect meaningful SiC substrate capacity toward data center applications, compressing availability for RF device manufacturers who share the same upstream substrate supply chain.
The pricing picture: two opposite forces
What makes this moment unusual is that GaN-on-SiC pricing is being pulled in two opposite directions simultaneously, and which direction dominates depends heavily on which part of the supply chain and which geography you are buying from.On the downward pressure side: rapid expansion of SiC capacity from Chinese players has led to significant price erosion — approximately a 30% drop in SiC wafer prices in 2024. Chinese entrants such as Tankeblue and Guangdong TySiC have grown rapidly by leveraging subsidized utilities and offering 6-inch wafers at USD 400–500, forcing incumbents to differentiate on defect density and technical support rather than price.
On the upward pressure side: high wafer costs, often USD 1,000 to USD 2,000 per unit, continue to slow adoption among cost-sensitive manufacturers for premium-tier substrates from Western suppliers — and the DoD prioritization mandate described above means that the remaining non-reserved foundry capacity at US and allied fabs is being priced at a premium. For a design team buying production-qualified GaN-on-SiC from a Tier-1 Western foundry without a long-term supply agreement already in place, the effective cost per wafer slot has increased, not decreased.
The bifurcation matters for T/R module designers: the low-cost Chinese substrates are not yet qualified for most defense radar applications, and yield rates for GaN and SiC materials remain lower than traditional silicon, impacting overall profitability — particularly at smaller volumes where a yield drop of 5–10% on an already expensive wafer run is a material cost event.
The 8-inch transition is creating a gap, not a bridge
The industry has been anticipating a smooth transition to 8-inch (200mm) GaN-on-SiC as the answer to both the capacity and cost problem. The reality is more complicated. Wolfspeed's 300-millimeter boule demonstration in January 2026 positioned the company to establish de facto standards, while SK Siltron plans 30,000 eight-inch wafers per month in Michigan by late 2026, promising regional supply security. But the qualification inertia is real: automotive and defense programs designed on 6-inch templates do not simply migrate to 8-inch without a full requalification cycle — and as fabrication yields improve on 8-inch wafers, a 15% price drop in GaN power units is anticipated, but that transition is still playing out, leaving 2026 in an awkward middle period where 6-inch capacity is tightening and 8-inch is not yet broadly available for production runs.For a radar program with a tape-out window in the next 12–18 months, this gap is not theoretical. It is a scheduling and budgeting reality.
What this means if you are designing a T/R module today
Three practical implications stand out.First, if your T/R module design depends on a specific GaN-on-SiC process node at a Western foundry — WIN Semiconductors' 250nm or 120nm processes, for instance — and you do not have a capacity reservation or multi-year supply agreement in place, the time to initiate that conversation is now, not at the pre-production stage. The foundries with the most relevant processes for radar FEM and HPA applications are operating closer to capacity utilization than their public communications suggest.
Second, the cost delta between a design using a Western-foundry qualified process (likely required for defense export compliance) and a Chinese-foundry alternative is narrowing on paper but widening in practice for programs that have specific substrate provenance requirements. Building that constraint into your BOM cost model early avoids unpleasant re-sourcing conversations late in the program.
Third, for teams evaluating whether to license production-ready GaN IP versus develop in-house: the foundry access problem does not disappear with in-house design capability. An IP block that comes with existing foundry tape-out data, characterized silicon, and an established production relationship with the process owner reduces the foundry slot negotiation from a zero-baseline conversation to a capacity expansion discussion — a meaningfully different starting position.
A practical note on VSI's IP approach to this problem
The foundry access challenge described above is one of the reasons VSI structures its GaN IP as production-ready hard macros rather than reference designs. Our VPF FEM family (X-band 250nm, Ku/Ka-band 120nm) and VPA/VPM HPA series were developed and characterized through WIN Semiconductors production runs — meaning the process qualification, DRC/LVS sign-off, and silicon performance data already exist. For a design team evaluating whether to license IP or develop in-house, that distinction matters in the current foundry environment: you are negotiating production capacity for a known-good process, not initiating a new qualification from scratch.If you are working on a T/R module program with a tape-out window in the next 12–18 months and want to see actual characterization data rather than simulated specs, the full IP catalogue is available on Design & Reuse. — including S-parameter models and integration documentation for each part number. For teams further along in evaluation, VSI's engineering team is available for direct technical discussion.
VSI — Viettel Semiconductor is a fabless semiconductor IP design company based in Hanoi, Vietnam, and the semiconductor arm of Viettel Group.
Technical inquiries: Email: minhnq43@viettel.com.vn / WhatsApp: +84965125018
