Calibrating Quantum Computing Activity in Financial ServicesI was invited to listen in on an…Read More
NoC Matters: Designing the Backbone of Next-Gen AI SoCsModern SoC design for artificial intelligence workloads has…Read More
From Wooden Boards to White Gloves: How FPGA Prototyping and Emulation Became Two Worlds of Verification… and How the Convergence Is UnfoldingFPGA prototyping and hardware emulation originated from two…Read More
When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the IncentivesMarc Evans, Director of Business Development & Marketing,…Read More
Mentor Graphics, a Siemens Business, has completed their acquisition of EDA company Avatar Integrated Systems. I recently spoke with Joe Sawicki, Executive VP of the Mentor IC EDA segment, about the acquisition strategy and IC Design platform goals for integration of the Avatar products.
Avatar (formerly ATopTech) focused… Read More
On the eve of the Innovative Designs Enabled by Ansys Semiconductor (IDEAS) Forum I spoke with Vic on a range of topics including his opening keynote: Accelerating Moore and Beyond Moore with Multiphysics. You can register here.
Vic Kulkarni is Vice President and Chief Strategist, Semiconductor Business Unit, Ansys, San Jose.… Read More
This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. The presentation covered here from Synopsys focuses on the… Read More
A checker tripped in verification. Is there a bug trace minimization technique to simplify manual debug? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series to highlight all the great research that’s out there in verification. Feel free to comment.
This month’s pick is Simulation-Based… Read More
Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, “UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV“. Verification engineers have been … Read More
Murilo Pilon Pessatti is an Electrical Engineer with a MSEE in Analog IC design. He studied in Brazil at São Paulo University (USP) and earned a masters at Campinas State University (UNICAMP). Murilo then moved to Lisbon in Europe to work for ChipIdea, in the early 2000’s when the smartphone era was just taking off.
“I… Read More
No-one likes being put on the spot and yet we all like a forecast…and as we all know, the only guarantee with a forecast is that it is wrong. Sports commentators have carved out a special niche for themselves with the ‘commentators curse’, just as they extol the virtues of an individual or a team, the sporting gods prove them wrong in … Read More
Many times i notice people “kind of afraid” of some protocol, trying to avoid the usage because “it’s complicated”, I decide to go in-depth in one and show that maybe it’s not so complicated after all. First challenge is choosing the protocol and decide about the Ethernet, because this protocol… Read More
Since the start of PROMS, PLDs and FPGAs we have learned the importance of programmability in modern semiconductor design. Today we have eFPGAs for “design adaptive” embedded programmability and that is what this webinar is all about.
Several key points are discussed starting with the Law of Accelerating Returns as it applies… Read More
It was a very late evening, perhaps 11 PM, on a warm summer night in 2008. Someone sent an email to info@cliosoft.com with a very odd question – why were we not listed in Wikipedia? The sender was a scientist working for the Lawrence Berkeley National Lab. Of course, this piqued my curiosity and I replied back asking why that concerns… Read More
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Disaggregating LLM Inference: Inside the SambaNova Intel Heterogeneous Compute Blueprint