In the recent DRAM jargon, “1X”, “1Y”, “1Z”, etc. have been used to express all the sub-20 nm process generations. It is almost possible now to match them to real numbers which are roughly the half-pitch of the DRAM active area, such as 1X=18, 1Y ~ 17, etc. At this rate, 14 nm is somewhere around
2026 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDACristian Amitroaie is the Founder and CEO of…Read More
Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V ExtensionThe rapid growth of signal processing workloads in…Read More
2026 Outlook with Richard Hegberg of Caspia TechnologiesTell us a little bit about yourself and…Read More
Siemens EDA Illuminates the Complexity of PCB DesignAs heterogeneous multi-die design becomes more prevalent, the…Read More
Accelerating Advanced FPGA-Based SoC Prototyping With S2CHaving spent a significant amount of my career…Read MoreCEO Interview: Anupam Bakshi of Agnisys
Although much of the EDA industry has consolidated into the “Big 3” players, there are still plenty of smaller vendors in the market. In the earlier days of EDA, it seemed that most startups existed only until they failed or did well enough to be acquired. The industry has changed; there are now a number of notable companies that have… Read More
ASML More Covid Concerns and Impact
- Covid related Revenue Rec causes rev/EPS miss
- Sharp order drop reflects H2 industry uncertainty
- EUV remains solid- Memory/Logic mix is better
Results were in line after correcting Covid Caused Revenue Rec issue-
ASML reported revenues of Euro3.3B and EPS of Euro1.79 as revenues from two EUV systems was not recognized, due to … Read More
The Official SemiWiki Virtual DAC 2020 Must See List!
This is going to be a record setting year for DAC content and attendance, absolutely!
My first DAC was in 1984 in Albuquerque New Mexico, right out of College, and I married my beautiful wife two months later. Thirty six DAC’s later I have four grown children, grandchildren, and the number one semiconductor design portal in the world.… Read More
In-Memory Computing for Low-Power Neural Network Inference
“AI is the new electricity.”, according to Andrew Ng, Professor at Stanford University. The potential applications for machine learning classification are vast. Yet, current ML inference techniques are limited by the high power dissipation associated with traditional architectures. The figure below highlights the … Read More
Mentor Cuts Circuit Verification Time with Unique Recon Technology
Most of us will remember the productivity boost that hierarchical analysis provided vs. analyzing a chip flat. This “divide and conquer” approach has worked well for all kinds of designs for many years. But, as technology advances tend to do, the bar is moving again. The new challenges are rooted in the iterative nature of high complexity… Read More
Talking Sense With Moortec … Ask Yourself a “Probing” Question?
Managing and controlling thermal conditions in-chip is nothing new and embedded temperature monitoring has been going on for many years. What is changing however, is the granularity and accuracy of the sensing now available to SoC design teams. Thermal activity can be quite destructive and if not sufficiently monitored can … Read More
Using AI to Locate a Fault. Innovation in Verification
After we detect a bug, can we use AI to locate the fault, or at least get close? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, through a paper in software verification we find equally relevant to hardware. Feel free to comment.
The Innovation
This month’s pick is… Read More
Novel DFT Approach for Automotive Vision SoCs
You may have seen a recent announcement from Mentor, a Siemens business, regarding the use of their Tessent DFT software by Ambarella for automotive applications. The announcement is a good example of how Mentor works with their customers to assure design success. On the surface the announcement comes across as a nice block and… Read More
A tour of Cliosoft’s participation at DAC 2020 with Simon Rance
As chip complexity grows, so does the need for a well-thought-out design data management strategy. This is a hot area, and Cliosoft is in the middle of it. When I was at eSilicon, we used Cliosoft technology to manage the design and layout of high-performance analog designs across widely separated design teams. The tool worked… Read More


AI Bubble?