Synopsys Announces Expanding AI Capabilities and EDA AI LeadershipIn the fast-paced semiconductor industry Synopsys has redefined…Read More
Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICsAn engineering change order, or ECO in the…Read More
The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)Introduction: The Historical Roots of Hardware-Assisted Verification The…Read More
Tessent MemoryBIST Expands to Include NVRAMThe concept of built-in self-test for electronics has…Read More
The Importance of Productizing AI. Everyday ExamplesKeeping up with the furious pace of AI…Read More
Seeking Alpha just published an article about Intel and Samsung passing TSMC for process leadership. The Intel part seems to be a theme with them, they have talked in the past about how Intel does bigger density improvements with each generation than the foundries but forget that the foundries are doing 5 nodes in the time it takes… Read More
The most vexing problem for physical implementation engineers is debugging errors due to power-ground “shorts”, as reported by the layout-versus-schematic (LVS) physical verification flow. The number of polygons associated with each individual grid is large – an erroneous connection between grids results in a huge number… Read More
-US Administration to “blacklist” SMIC- Cutting off ALL US help
-A slow death versus a quick death (unlike Jinhua)
-There is enough time on way out door to leave scorched earth
-Reports in the Media about SMIC being “Blacklisted”
It has been widely reported that SMIC will be added to the US “Blacklist”… Read More
A few months ago, I posted a piece about PLDA expanding its support for two emerging protocol standards: CXL™ and Gen-Z™. The Compute Express Link (CXL) specification defines a set of three protocols that run on top of the PCIe PHY layer. The current revision of the CXL (2.0) specification runs with the PCIe 5.0 PHY layer at a maximum… Read More
Can machine learning be combined with formal to find rare failures in analog designs? ML plus formal for analog – neat! Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series on research ideas. Here an idea from analog simulation sampling. Feel free to comment.
This month’s pick… Read More
On December 2, 2019, I posted a SemiWiki article entitled “ASML Will Take Semiconductor Equipment Lead from Applied Materials in 2019.”Since losing its dominance for the first time since 1990 in 2019, Applied Materials is poised to lose its retake the 2020 lead in the semiconductor equipment market. ASML led the… Read More
Ongoing investigations of EUV stochastics [1-3] have allowed us to map combinations of critical dimension (CD) and pitch which are expected to pose a severe risk of stochastic defects impacting the use of EUV lithography. Figure 1 shows a typical set of contours of fixed PNOK (i.e., the probability of a feature being Not OK due… Read More
With the complexity of transistors at an all time high and growing foundry rule decks, fabless companies consistently find themselves in a game of catch up. Semiconductor designs require additional compute resources to maintain speed and quality of development. But deploying new infrastructures at this current speed is a tall… Read More
SRAM is the workhorse for on-chip memories, valued for its performance and easy integration with standard processes. The needs of wearable, IoT and AI SOCs have put a lot of pressure on the requirements for all on-chip memories. This is perhaps most evident in the area of power. AI chips that rely heavily on SRAM register files are… Read More
You may have heard of Folding at Home. It’s a very creative way that a bioengineering team, based at Washington University in St Louis, are modeling the process of protein folding. Greg Bowman, an associate professor of biochemistry and biophysics at the university directs the project and presented at Arm DevSummit this year. … Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet