CDC Verification for Safety-Critical Designs – What You Need to KnowVerification is always a top priority for any…Read More
Ceva Unleashes Wi-Fi 7 Pulse: Awakening Instant AI Brains in IoT and Physical RobotsIn the rapidly evolving landscape of connected devices,…Read More
Adding Expertise to GenAI: An Insightful Study on Fine-TuningI wrote earlier about how deep expertise, say…Read More
EDA Has a Value Capture Problem — An Outsider’s ViewBy Liyue Yan (lyan1@bu.edu) Fact 1: In the…Read More
WEBINAR: How PCIe Multistream Architecture is Enabling AI ConnectivityIn the race to power ever-larger AI models,…Read More
This is another level-up story, a direction I am finding increasingly appealing. This is when a critical supplier in the electronics value chain moves beyond islands of design automation to provide an integrated solution for the front-to-back design for capabilities now essential for automotive and industrial automation … Read More
Standards help our EDA and IP industry grow more quickly and with less CAD integration efforts, and IP-XACT is another one of those Accellera standards (1685-2009) that is coming of age, and enabling IP reuse for SoC design teams. Here at SemiWik, we’ve been writing about Defacto Technologies and their prominent use of IP-XACT… Read More
We used to be comfortable with the idea that the worlds of logical design and physical implementation could be largely separated. Toss the logical design over the wall, and the synthesis and P&R teams would take care of the rest. That idea took a bit of a hit when we realized that synthesis had to become physically aware. The synthesis… Read More
Recently, a patent application from TSMC [1] revealed target EUV doses used in the range of 30-45 mJ/cm2. However, it was also acknowledged in the same application that such doses were too low to prevent defects and roughness. Recent studies [2,3] have shown that by considering photon density along with blur, the associated shot… Read More
Verification is a complex task that takes the majority of time and effort in chip design. At Veriest, as an ASIC services company, we have the opportunity to work on multiple projects and methodologies, interfacing with different experts.
In this “Verification Talks” series of articles, we aim to leverage this unique… Read More
Frequent SemiWiki readers are aware of the growing significance of heterogeneous multi-die packaging technologies, offering a unique opportunity to optimize system-level architectures and implementations. The system performance, power dissipation, and area/volume (PPA/V) characteristics of a multi-die… Read More
Lam- good quarter but supply chain headwinds limit upside
Memory seems OK for now but watch pricing
China will also weaken which may add caution
Performance remains solid as does technology prowess
The yellow caution flag in the Semi race impacts Lam as well
As we suggested two weeks ago and saw with ASML this morning, supply chain… Read More
ASML great QTR but supply chain will limit acceleration
Products are most complex with most extensive supply chain
Long term position fantastic but investors will be nervous
300M pushouts in DUV with EUV still on track
Good quarter but yellow caution flag is out for supply chain concerns
ASML reported great revenues of Euro5.2B… Read More
Dan and Mike are joined by Kim McMahon, Director of Visibility & Community Engagement, RISC-V International and Rob Mains Executive Director, CHIPS Alliance. Kim and Rob are working with individuals and companies to promote diversity and inclusion in the open hardware industry. We explore their strategies, goals and plans… Read More
Jothy Rosenberg is a serial entrepreneur, founding nine different startups since 1988, two of which sold for over $100M. Currently, he’s the Founder & CEO of Dover Microsystems, the first oversight system company. Earlier in his career, Jothy ran Borland’s Languages division where he managed languages like Delphi, C++,… Read More
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AI RTL Generation versus AI RTL Verification