Synopsys Announces Expanding AI Capabilities and EDA AI LeadershipIn the fast-paced semiconductor industry Synopsys has redefined…Read More
Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICsAn engineering change order, or ECO in the…Read More
The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)Introduction: The Historical Roots of Hardware-Assisted Verification The…Read More
Tessent MemoryBIST Expands to Include NVRAMThe concept of built-in self-test for electronics has…Read More
The Importance of Productizing AI. Everyday ExamplesKeeping up with the furious pace of AI…Read More
As processor architecture and design development becomes completely liberated with open-source RISC-V instruction set architecture (ISA), the race to get RISC-V silicon in our hands has increased massively. We have no doubt that in next 5 years, we will see RISC-V based laptops and desktops in the market. But would these processors… Read More
Dan is joined by Ying Chen, VP of marketing & international sales at S2C. Dan and Ying explore the various uses and benefits of FPGA-based prototyping, including the different architectures available and cloud access.
Mr. Chen is a dynamic technologist with over 23 years of technical and business experiences in digital … Read More
It was my pleasure to meet Veerbhan Kheterpal. Veerbhan has founded three technology companies and has full stack expertise spanning software to silicon across Edge & Datacenter applications. Currently, he is a CEO & co-founder of quadric.io, a company that has created a new processor architecture for high performance… Read More
Roots of trust can’t prevent attacks through side-channels which monitor total power consumption or execution timing. Correcting weakness to such attacks requires pre-silicon vulnerability analysis. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO)… Read More
Back in 2020 I first learned from Synopsys about how they had engineered a better way to do optimize layouts on digital designs by using machine learning techniques, instead of relying upon manual approaches. The product was named DSO.ai, standing for Design Space Optimization, and it produced a more optimal floor-plan in less… Read More
One of the career Intel employees (33+ years) that Pat Gelsinger brought back is Stuart Pann. Stuart is now the Senior Vice President of the Intel Corporate Planning Group. He does not have direct foundry experience but he certainly knows Intel and Pat so it will be interesting to see where this goes.
Stuart recently penned an article… Read More
Humans certainly have always had an aesthetic preference for symmetry. We also see symmetry showing up frequently in nature. The importance of symmetry in electronic designs has been apparent for decades. There are a host of analog structures that require balanced layout. For instance, these include differential pairs and … Read More
Do you use Tile or other Bluetooth tracking devices? If so, you know that such devices, attached to your car keys or wallet, created a small stir. A way to track down something you can’t find. Very neat but hardly revolutionary. One of those consumer tchotchkes as likely to be handed out as trade-show swag as purchased.
So why did Apple… Read More
A company that gets its products to market first stands to gain a competitive edge in the market place. This is even more so in the highly competitive and innovative semiconductor industry. At the same time, designing chips is a very challenging task that involves iterative steps that are computation, memory and storage intensive.… Read More
Cadence invests heavily in the development of their Tempus Timing Signoff Solution due to its importance in the SoC design flow. I recently had a discussion on the topic of the most recent Tempus update with Brandon Bautz, senior product management group director in the Digital & Signoff Group, and Hitendra Divecha, product… Read More
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Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet