EDA Has a Value Capture Problem — An Outsider’s ViewBy Liyue Yan (lyan1@bu.edu) Fact 1: In the…Read More
WEBINAR: How PCIe Multistream Architecture is Enabling AI ConnectivityIn the race to power ever-larger AI models,…Read More
A Six-Minute Journey to Secure Chip Design with CaspiaHardware-level chip security has become an important topic…Read More
Lessons from the DeepChip Wars: What a Decade-old Debate Teaches Us About Tech EvolutionThe competitive landscape of hardware-assisted verification (HAV) has…Read More
Think Quantum Computing is Hype? Mastercard Begs to DisagreeJust got an opportunity to write a blog…Read More
As the complexity of the chip-package-system (CPS) interactions has increased, the tradeoffs in doing a power and noise analysis has had to gradually increase. As is so often the case in semiconductor designs, issues first arise as second-order effects that can largely be ignored but each process node makes the problem worse … Read More
DAC is less than a month away, June 6-8th for the tradeshow, longer depending on what other events you might also be attending. Apache is in booth 2448 (marked in red on the DAC floorplan map.
Many of the presentations at the Apache booth will be customers (such as ARM, Xilinx, ST Ericsson, GlobalFoundries and TSMC) discussing various… Read More
Introduction
Today Cadence announced at the Embedded Systems Conference something of interest to systems designers.
What’s New?
The Rapid Prototyping Platform and Virtual System Platform are what’s new, and they intend to enable and automate concurrent hardware and software development. I can remember Mentor… Read More
Although there has been always a strong relationship between Kilopass and Chartered Semiconductor, this relationship has been even enhanced after the acquisition of Chartered by GLOBALFOUNDRIES, allowing Kilopass’s customers to integrate NVM IP on advanced technology nodes, down to 40nm or even 28nm in the near future.
Before… Read More
Introduction
IC designs go through a layout process and then a verification of that layout to determine if the layout layer width and spacing rules conform to a set of manufacturing design rules. Adhering to the layout rules will ensure that your chip has acceptable yields.
At the 28nm node a typical DRC (Design Rule Check) deck will… Read More
The corporate raiders are still throwing rocks at Mentor Graphics. I have followed this reality show VERY closely and find their latest assault seriously counterproductive. Disinformation is common in EDA but I expected more from Carl Icahn and the Raiderettes. They are quite the drama queens. Here is a billion dollar question:… Read More
TSMC continues to drive the economic recovery with impressive Q1 numbers and an even more impressive Q2 and Q3 outlook. TSMC is my economic bellwether due to its diverse customer base and shear volume of consumer electronics silicon. The big surprise in the 1 hour Q1 conference call is a new Giga Fab (#15) ground breaking this year… Read More
I was at Mentor’s u2u (user group) meeting and one of the keynotes was by Ivo Bolsens of Xilinx. The other was by Wally Rhines and is summarized here.
Ivo started off talking analogizing SoCs as the sports-cars of the industry (fast but expensive), and FPGAs as the station wagons (not cool). In fact he even said that when Xilinx… Read More
I was at Wally’s u2u (Mentor user group) keynote yesterday. The other keynote was by Ivo Bolsens of Xilinx and is here. He started off by looking at how the semiconductor industry has recovered and silicon area shipments are now back on trend after a pronounced drop in 2009 and revenue has followed. Finally the semiconductor… Read More
Have you ever had the experience where you look up some unusual word in the dictionary since you don’t remember seeing it before. And then, in the next few weeks you keep coming across it. Twice in the last week I have been in presentations about the economics of putting die onto silicon interposers and the possibility of a new… Read More
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AI RTL Generation versus AI RTL Verification