In just 20 days you can get an update on four Mentor Graphics tools as used in the TSMC Open Innovation Platform (OIP). Many EDA and IP companies will be presenting along with Mentor, so it should be informative for fabless design companies in Silicon Valley doing business with TSMC.
San Jose Convention Center
Tuesday, October 16, 2012
A Platform for the CoWoS Reference Flow
The first phase of 3DIC adoption will be based on silicon interposers. Designing multi-die systems using this technology introduces new challenges for the EDA design flow. This session will provide an overview of the key challenges of 3DIC at the planning, optimization, implementation, verification, and test stages of the design flow. We will also describe how EDA tools are being extended to address these issues:
- Planning, assembling and optimizing interposer-based designs
- P&R support for TSV, microbumps, silicon interposer redistribution layer (RDL) and signal routing
- Multi-die integration and the need for a 3DIC cockpit
- New extraction challenges and modeling of silicon interposers and through silicon vias (TSVs)
- Test infrastructure insertion to support test access to die test features within the package
- Testing TSVs, interposers and inter-die connections, and reusing die patterns after packaging
We will also hint at the future roadmap for IC/package co-design and the evolution to integrated IC, package and PCB design environment to enable true “vertical scaling.”
Finding and Fixing Double Patterning Errors in 20nm Design
Double patterning brings a new set of design constraints to the 20nm node and it has caused designers to get very concerned about how they find and deal with DP related violations. In this presentation, we will explain the kinds of violations that are unique to double patterning design and how the jointly developed tools with Mentor and TSMC help identify them and aide the designer in fixing them. Examples and best practices methods will also be discussed.
Improved Design for Reliability Using Calibre PERC
Verification of 20nm designs is expected to bring significant challenges. A robust verification methodology that addresses circuit reliability is increasingly difficult. At 20nm, new devices that incorporate thin oxides are less robust and more subject to electrical overstress (EOS) failures. The increased use of mixed-signal and multi-voltage design techniques also increases the likelihood that transistors could be implemented in an incorrect voltage domain. Preventing long term electrical failure means IC designers should utilize new techniques to validate ESD structures, protect against EOS, manage multiple power domains, and carefully balance sensitive analog circuits. This session describes these challenges and how MediaTek is usng Calibre PERC to address IC design for reliability issues.
Automated Approach for Waiving Physical Verification Errors at IP
Redundantly reviewing recurring errors Custom and third-party IP integration can slow down SoC verification. An automated waiver management methodology enables design and verification teams to specify and process a variety of design rule waivers, reducing debugging time and improving SoC results. This technology provides customizable control to waive errors only under certain conditions or constraints.