We’re plagued by acronyms in this business. Wikipedia defines RTL as follows: “In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.” This is kind of wordy for my taste. I’ve always thought of an RTL description as “what” the circuit does and not necessarily “how” it does it.
Increasing complexity has forced designers to retreat to higher levels of abstraction. You just can’t deal with all the issues at the gate level anymore, time and money won’t allow it. This trend has created a new EDA market segment for RTL design tools. RTL design has been around for a long time – over 20 years – but the market has seen some significant growth in the last 10 years, owing to the need to deal with design abstraction at a higher level due to complexity. Another way to think about this market is that it’s the pre-synthesis part of the design flow. Everything you do at RTL is basically intended to maximize the chances that the synthesis/place & route flow will go smoothly and there won’t be any surprises or fire drills. Things like lack of timing closure, not fitting in the package or not meeting the power budget all constitute fire drills in this context.
The Big 3 offer RTL design tools, but so do a whole host of other smaller companies. There are quite a few startups that focus exclusively on this market. If you think about it, this makes sense. The back-end flow is dominated by the Big 3, and that flow is becoming increasingly commoditized. It’s not a good place for a small company to try and break into. On the other hand, the design flow above the back-end has plenty of growth opportunity. To get another perspective on this market and how it has evolved, I turned to a guy who has been at it for quite a while – Ajoy Bose. He is the founder of Atrenta, the company that builds SpyGlass. This product has become something of a de-facto standard for RTL design. It’s so popular, the company actually re-branded themselves as “the SpyGlass Company” at DAC this year.
Ajoy is no stranger to RTL design, having led the team that developed the Verilog simulator at Cadence in its early days. When I asked Ajoy how Atrenta got started, I was surprised at the answer. In the late 1990’s, he was running a services company called Interra. One of their projects was to work with a large semiconductor company to help them develop a better methodology for IP reuse. During that project, they developed a piece of software that looked at a synthesizable description of an IP to see if it had any design constructs that would be inherently difficult to reuse. The project was a big success, and Ajoy and the team realized they were on to something. Could that software be generalized and made available as a product, and not just service-ware? The team thought so, and so Atrenta was born in 2001. I’m not sure if it was luck or extreme wisdom, but the Interra contract allowed the company to retain rights to the software they built for that services customer. That came in handy. Atrenta productized the code, and a new generation of RTL linting was born in the form of SpyGlass.
It seems that testability analysis was added next, then clock domain crossing (CDC) analysis followed by power and so on, creating a complete RTL platform all under the brand of SpyGlass. Today, there are probably a dozen companies all competing for your RTL analysis dollars. Some specialize in power reduction, some focus on CDC analysis and others on timing constraints. Everybody seems to have a linter. It’s good to see this level of competition from smaller companies. It suggests maybe there is growth opportunity in EDA after all.
I wondered where the next level of growth could come from in this market, so I went back to Atrenta. When I asked Ajoy that question, he paused for a moment and then said “if you’re looking for growth, never look down. Look sideways or look up.” It took me a minute, but I got the message. Sideways means adding more or better tools to the RTL flow. Different approaches to simulation and verification come to mind as one area for growth. Atrenta’s recent acquisition of NextOp looks like that kind of play. When you look up, there are lots of opportunities. The level above RTL includes things like SystemC. Anyone up for an integrated high-level synthesis to gates flow? I’d say there’s still a lot of work to do on that one.
Links to software is another interesting one. What if your RTL description can create a model that is accurate enough and fast enough to run software? You could then iterate the hardware design based on the way the software performs. Real hardware/software co-design. I suspect whoever gets that right will make some serious money.
Also see: A Brief History of RTL