WP_Term Object
(
    [term_id] => 34
    [name] => Ansys, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 214
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 214
    [category_description] => 
    [cat_name] => Ansys, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)
            
ANSYS IDEAS logo
WP_Term Object
(
    [term_id] => 34
    [name] => Ansys, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 214
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 214
    [category_description] => 
    [cat_name] => Ansys, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)

Chip Aware System Design

Chip Aware System Design
by Paul McLellan on 09-24-2012 at 5:45 pm

On Wednesday this week Ansys/Ansoft/Apache are presenting a new webinar Chip Aware System Design. It is presented by Dr Steven Gary Pytel Jr of the Ansoft part of Ansys, and Matt Elmore of the Apache subsidiary. The topics that will be covered include:

  • Power Delivery Network (PDN) design requirements
  • ABCD Matrix theory
  • SYZ Matrix theory
  • Chip-level Extraction
  • Effect of Chip inclusion on time and frequency domain system simulations

 The webinar is in two parts, the first part fairly theoretical and mathematical (as you can see from the above list), that gives the foundation for analysis, especially frequency domain analysis. The second part takes that theory and uses it for practical analysis of power delivery networks.

The goal is that by the end of the webinar, attendees will be able to:

  • gave a basic understanding of impedance, transmission and scattering parameters
  • perform basic analyses on return and insertion loss
  • understand the impact of chip parasitics in both time and frequency domains
  • create and analyze “what if” test cases for real chip, package and PCB designs


The webinar is at 11am Pacific Time on Wednesday, 1pm on the east coast and corresponding times elsewhere. Pre-registration is here.

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