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Verification Engineer

Verification Engineer
by Admin on 11-11-2022 at 1:45 pm

Website Secure-IC

Your role and responsibilities

Within the R&D team, you will participate to IPs, subsystem and SOC verification.

Also, you will be involved in Secure-IC development steps as follow:

  • Test plan creation.
  • Design and verification of standalone VIPs, based on standard or custom protocols.
  • Design and verification of behavioral models (C or SystemVerilog).
  • Conduct verification at IP and/or SOC level
  • Coverage and reports analysis
  • Support to design, architecture and integration teams

Education, Experience & Skills

  • We are requiring an Engineer diploma in microelectronics or equivalent diploma level for this position;
  • A first experience in verification is mandatory.
  • A good knowledge of standard verification methodology (UVM and SystemVerilog) is mandatory.
  • A good knowledge of data management system (GIT, SVN, …) is mandatory
  • You are fluent in English to join a multicultural company;
  • A good knowledge in C/C++ could be a plus as well as a good practice of scripting (Python, Perl, TCL, sh) could be a plus.

At Secure-IC, we guarantee equal opportunities and diversity, which is why our position is open to people with disabilities. Only skills and motivation make the difference!

Apply for job

To view the job application please visit www.secure-ic.com.

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