Advanced Insights Ep. 3: Dr. Y. J. Mii on 2nm and Beyond
- Thread starter hskuo
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Y.J. did a great job today at the Symposium. This was very fluffy but I get his point about DTCO, it is something TSMC can do since they have the cooperation of just about every semiconductor company around the world.
I wonder why AMD is doing this? Seems low budget but they do have a lot of subscribers.
I wonder why AMD is doing this? Seems low budget but they do have a lot of subscribers.
Kind of disappointing to hear that TSMC is doing two teams with 5-7 years of development. That would mean the earliest we can expect A14 (or I guess in light of the renaming of N2+BSPD to A16, that they are more likely to go with A12) is 2028, and worst case 2030. If TSMC lets the gaps between nodes get that big it feels like they will need to make bigger leaps, and the HVM sites will need to make more improvements faster so that TSMC can have good PPAC improvements during the long drought between nodes.
Can you restate this comparing Intel's foundry offering versus TSMC? Compering chiplets designed inside Intel to many outside customers designing full chips on TSMC processes is naive.
Yeah I wasn't super clear about that. It wasn't really a jab at technological competitiveness as that is a remains to be seen sort of thing given intel hasn't talked about what 14A brings over 18A and even then we need to wait until 2026 just to see how the different aspects of N2 stack up vs 18A and SF2 (assuming intel and Samsung deliver on time). My "disappointment" was in the sense of me wondering if TSMC was going back to a 2 year cadence (which we now know isn't the case). Technically speaking if it wasn't for N3 products coming out in 2023 instead of 2022 the gap between N3 and N2 would have been a whole 4 years! This is a massive slow down from from the 2 year cadence we are used to for most of TSMC's 40 year history.
All in all I don't really consider this a good or bad thing (it just is). If that is how long it takes to deliver an excellent process technology then so be it. But you have to remember I am a process engineer Dan. While I understand the importance of chip design and PDKs, it isn't a personal interest for me a chemical engineer. So as someone who really enjoys the process tech and just wants to see "the new shiny toy", it is disappointing for me to see TSMC slow down. But who knows maybe A12 will really knock my socks off.
I think your socks are safe until maybe CFETs. Intel and TSMC talk more about packaging than process technology at these events. Moore's Law continues due to everything except process technology. TSMC talked more about their version of BSPD which they call Super Power Rail. The name alone says a lot, it is SUPER! Those Conventional Power Contact people are in big trouble!