Manager I, Analog Design

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Analog Design Manager

Job Responsibilities:

• Lead a small team of 3 to 4 mixed-signal circuit designers with varying experience in the successful completion of a leading-edge High Speed SerDes design
• Review SerDes standards and architecture documents to develop analog sub-block specifications.
• Identify and refine circuit implementations to achieve optimal power, area and performance targets.
• Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
• Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
• Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
• Review simulation data for peer and prepare customer reviews.
• Mentor and Review the progress of designers in your team.
• Document design features and test plans.
• Consult on the electrical characterization of your circuit within the SerDes IP product.

Job Requirements:

• PhD with 5+ years, or MSc with 8+ years of SerDes/High-Speed analog design experience
• Managerial or Team Lead experience of 2+ years
• In-depth familiarity with transistor level circuit design – sound CMOS design fundamentals.
• Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
• Detailed design experience with several of the following SerDes sub-circuits:
  receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
• Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
• Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
• Experience with EDA tools for schematic entry, physical layout, and design verification.
• Knowledge of SPICE simulators and simulation methods.
• Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
• Experience with TCL, Perl, C, Python, MATLAB.