Design & EDA Collaboration Advances Mixed-Signal Verification through VCS AMS

Last week it was a rare opportunity for me to attend a webinar where an SoC design house, a leading IP provider and a leading EDA tool provider joined together to present on how the tool capabilities are being used for advanced mixed-signal simulation of large designs, faster with accuracy. It’s always been a struggle to combine design and simulation of analog and digital together for complex SoCs and several techniques are being adopted – AoT (Analog-on-Top), DoT (Digital-on-Top) and MSoT (Mixed-Signal-on-Top) topologies, analog and mixed-signal language support such as Verilog-A, Verilog-AMS and others, mixed-signal simulators and unified testbenches. This webinar provided a real insight into how the mixed-signal verification issues are being tackled by utilizing advanced features of VCS AMS.

It was awesome to know about the advances taking place in semiconductor design space at ever shrinking nodes of fabrication and how EDA tools are enabling those design and verification needs with everything being together on a single chip.

ARM, the top IP provider with significant investment in their physical IP portfolio, is providing great leadership in advancing process technology through accelerated adoption of lower process nodes with complex technologies such as FinFET. ARM provides complete library of GPIO (General Purpose I/O) cells with fully programmable bi-directional IO cells, complete I/O system with I/O ring and ESD protection and physically optimized for single and multiple rows and other requirements with multiple cell views, extensively validated to provide high quality IPs.

ARM’s significant challenges for keeping functional equivalence between Verilog and Spice were calibration of Verilog view against Spice netlist, allowing digital testbench and assertions to check for equivalence for corresponding Spice netlist, passing ‘X’ and ‘Z’ states to Spice netlist and bringing back I/O response in Verilog, and power-aware functionality validation. They have been able to successfully address these challenges and gain high productivity by using advanced features of VCS AMS such as ease of toggling between Verilog, Spice and Verilog-AMS views for the same cell without modifying the original netlist, automatic insertion and optimization of interface elements (A/D, D/A), improved functional coverage and robust simulation reliability. An enhanced debugging environment with provisions for combining or separating outputs of analog and digital waveform files, taking signals from I/O blocks to Verilog and comparing against expected output and propagating ‘Z’ state from I/O cells to Verilog provides great ease in debugging, thus adding further into verification productivity.

With the seamless execution, support of power-aware Verilog model validation, first-time pass without any convergence issue and predictable A/D and D/A conversions in VCS AMS, ARM has been able to successfully deploy their design project on FinFET process. Venkatesh B K from ARM spoke in great detail about their technologies and methods to counter the challenges of mixed-signal verification and future expectations.

Pierluigi Daglio from ST Microelectronicstalked at length about their methodology to accelerate mixed-signal verification through the use of Assertions and Save-and-Restore features of VCS AMS. Before I go into the details of ST stuff, let me talk about VCS AMS which was introduced by Helene Thibieroz from Synopsys.

VCS AMS combines VCS and CustomSim to provide one of the fastest mixed-signal verification solutions with multi-core support (5x performance gain at transistor level accuracy with 16 cores for RF, RX design with 300K transistors) and Save-and-Restore features. It supports all types of topologies and configurations and various languages at analog (Spice, Verilog-A and others), digital (Verilog, VHDL, SystemVerilog, SystemC, Matlab) and mixed-signal (Verilog-AMS, Real Number Model, SystemVerilog Nettype) levels supporting complex integration schemes. It has an excellent netlist driven debug environment ensuring the design not to fail during simulation; because A/D interface elements (a major cause of failures) are inserted automatically with proper mapping of ports and directions, correct positioning and optimization for speed and accuracy. The testbench utilizes UVM methodology by extending it for analog that enables digital testbench technology for mixed-signal and accelerates development with lower risk. With the support of AMS assertions, constrained-random stimulus and checkers, it excellently fits into metric-driven verification methodology and coverage driven verification planning. Advanced low power verification capability has been added into VCS AMS by leveraging VCS native low power technologyand support of UPF formatfor mixed-signal. It also provides static checking with Circuit Check (CCK) to detect problems such as missing level shifter, stacking MOSFET between rails, and leakage path induced by gated power. Thus VCS AMS provides a very comprehensive verification solution for large mixed-signal designs constituting complex SoCs.

Coming to back to ST, it uses VCS AMS Assertions and Save-and-Restore features very excellently to gain superior productivity in simulation and verification of their large IPs, macro cells and AMS systems. They verify complex designs with the mix of netlist configurations for digital (Verilog/VHDL post synthesis) and analog (pre-layout, post-layout), operating conditions for digital (min/max delay) and analog (TYP, SSA, FFA) and different modes (user mode, test mode) of operation.

ST in this application used embedded memory with digital and analog circuitry together for verification. It used AoT topology and digital testbench. A ROM was inserted for comparing the memory content with the content in ROM for automatic score boarding.

For automatic score boarding, automatic checks on memory content are done through assertions and any failing match can be clearly seen in simulation results report and waveform.

The Save-and-Restore is an excellent feature which allows running a simulation, saving result, changing something (netlist or setup) and running another simulation with different scope. This technique is typically used for running multiple functional simulations on the same design after the power up and saving significant amount of simulation time. Multiple modes of simulation can be alternated at successive steps of simulation as needed. In real applications, for example memory, operations such as ‘read’, ‘program’ and ‘erase’ can be repeated in succession.

Multiple simulation runs can be executed by forcing a test selector variable via UCLI. In the above picture, the blue waveform is for boot operation, green for test1 and red for test4.

Interested designers and verification engineers can attend the webinarto gain detailed insight into actual operations through several examples, simulation results and waveforms. It’s a full 53 minutes webinar with interesting Q/A at the end. To mention a few; in the face of wide variety of process technologies (including IoT) and challenge for Spice simulation to keep pace with them, expectations from EDA vendors is to provide all Spice simulators integrated across process technologies without any problems of interfaces and providing predictable and reliable results; it’s expected that more advanced A/D interface support with increased coverage and maximum level of UPF support to manage power intent becomes available. There were other challenges, solutions and expectations which can be heard in the webinar. It’s a very interesting and useful webinar for SoC verification professionals.

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