Tag: equivalence

5X Faster Equivalence Checking with Formality ML-driven DPX

5X Faster Equivalence Checking with Formality ML-driven DPX
by Admin on 05-24-2022 at 4:01 pm

Synopsys Webinar | Thursday, June 9, 2022 | 10:00 – 11:00 a.m. Pacific

Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation

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Design & EDA Collaboration Advances Mixed-Signal Verification through VCS AMS

Design & EDA Collaboration Advances Mixed-Signal Verification through VCS AMS
by Pawan Fangaria on 09-07-2014 at 8:00 pm
Categories: Arm, EDA, Foundries, IP, STMicroelectronics, Synopsys

Last week it was a rare opportunity for me to attend a webinar where an SoC design house, a leading IP provider and a leading EDA tool provider joined together to present on how the tool capabilities are being used for advanced mixed-signal simulation of large designs, faster with accuracy. It’s always been a struggle to combine design… Read More

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How to Reduce Maximum Power at RTL Stage?

How to Reduce Maximum Power at RTL Stage?
by Pawan Fangaria on 08-16-2014 at 8:30 am
Categories: EDA

Of course that reduction has to stay throughout the design cycle up to layout implementation and fabrication. Since the advent of high density, mega functionality SoC designs at advanced nodes and battery life critical devices played by our fingertips, the gap between SoC power requirement and actual SoC power has only increased.… Read More