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Cadence & ARM Optimize Complex SoC Performance

Cadence & ARM Optimize Complex SoC Performance
by Pawan Fangaria on 12-03-2013 at 3:00 pm

Now a day, a SoC can be highly complex, having 100s of IPs performing various functionalities along with multi-core CPUs on it. Managing power, performance and area of the overall semiconductor design in the SoC becomes an extremely challenging task. Even if the IPs and various design blocks are highly optimized within themselves, the SoC design as a whole may not provide optimum results if not architected well. The central idea to gain the best performance is in how best all these components are interconnected together. So, how to get that optimum arrangement in a large solution space which can have several possibilities?

[A typical SoC configuration]

In the above SoC configuration there are ARMCoreLink advanced System IP components connected to CadenceDatabahn DDR controller. These advanced System IP components provide many choices to designers for interconnection along with other important solutions such as cache coherency, thus enabling them to rapidly explore the design space and determine the best optimized configuration.

Cadence and ARM have developed an efficient solution for SoC integration where ARM’s highly configurable IP components are used in Cadence’s Interconnect Workbench environment. ARM’s CoreLink NIC-400 can have many master and slave interfaces of AMBA family, i.e. AHB, AXI, APB and AXI4 which again can have configurable address space, width and clock speeds. Then there are Quality of Service (QOS) and Virtual Networks (QVN) which provide mechanisms for bandwidth and latency management. To manage routing congestion, there are Thin Links at user disposal for any special point-to-point connection.

[AMBA Designer – Configuration of a complex NIC-400 interconnect]

ARM provides a CoreLink AMBA Designer for user to easily and interactively select implementation options for the best configuration. A design topology having appropriate size and switch matrix with sufficient throughput and low latency must be selected from the rest.

After quickly architecting the SoC, the immediate challenge is to verify how this complex arrangement is going to perform under different scenarios of a full SoC context. This is where Cadence Interconnect Workbench comes into picture and provides many different types of “what if?” analysis capabilities.

[Top – Latency distribution, Bottom – One-click waveform debug of slow transactions]

Above is an example of latency distribution of a group of simulations. It clearly shows that writes are quicker than reads. Slower transactions can be debugged further by right-clicking and launching Cadence’s SimVision tool.

Interconnect Workbench provides comprehensive capabilities for quickly capturing and analysing cycle-accurate performance of the architecture. AMBA Designer generates the RTL as well as IP-XACT XML file that matches the design. Interconnect Workbench reads the IP-XACT file and automatically generates a UVM testbench in either ‘e’ or ‘SystemVerilog’.

[Interconnect Workbench generated testbench]

The IP-XACT descriptions of System IP cores enables Interconnect Workbench to provide performance analysis for interconnect components as well as cycle-accurate models of DDR controllers. Above figure shows the testbench of a SoC core along with DDR controller.

It’s imperative that with flexible tools to select appropriate architectures, clock schemes, memory and cache sizes, power domains and other required configurations, semiconductor design integrations can be accelerated to meet the time-to-market challenge. A detailed description of ARM’s CoreLink, AMBA Designer and Cadence’s Interconnect Workbench is provided in a whitepaperat Cadence website. It’s an interesting read to know more about recent advances in System IP components and interconnect performance optimization in SoCs.

More Articles by Pawan Fangaria…..

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