Maximize Bandwidth in your Massively Parallel AI SoCs?

Maximize Bandwidth in your Massively Parallel AI SoCs?
by Daniel Nenni on 07-20-2018 at 12:00 pm

Artificial Intelligence is one of the most talked about topics on the conference circuit this year and I don’t expect that to change anytime soon. AI is also one of the trending topics on SemiWiki with organic search bringing us a wealth of new viewers. You may also have noticed that AI is a hot topic for webinars like the one I am writing… Read More


CES: An Exhibitor’s Takeaway

CES: An Exhibitor’s Takeaway
by Bernard Murphy on 02-06-2018 at 7:00 am

There are few tech promises these days as prominent as those surrounding driverless cars (trucks, buses, …). But thanks to always-on media amplifiers, it’s not always easy to separate potential from reality. I recently talked to Kurt Shuler, VP Marketing at Arteris, who shared his view after returning from this year’s CES. Kurt… Read More


NetSpeed Bridges the Gap Between Architecture and Implementation

NetSpeed Bridges the Gap Between Architecture and Implementation
by Mitch Heins on 12-29-2016 at 11:30 am

This is part II of an article covering NetSpeed’s network-on-chip (NoC) offerings. This article dives a little deeper into what a NoC is and how NetSpeed’s network synthesis tool, NocStudio, helps system architects optimize a NoC for their system-on-a-chip (SoC) design.

Traditionally IC designers have used proprietary buses,… Read More


NetSpeed Leverages Machine Learning for Automotive IC End-to-End QoS Solutions

NetSpeed Leverages Machine Learning for Automotive IC End-to-End QoS Solutions
by Mitch Heins on 12-24-2016 at 4:00 pm

A couple of weeks back I wrote an article about the use of machine learning and deep neural networks in self-driving cars. Now I find that machine learning is also being applied to help build advanced end-to-end QoS (quality of service) solutions for the automotive IC market. With the advent of self-driving cars comes requirements… Read More


Optimizing memory scheduling at integration-level

Optimizing memory scheduling at integration-level
by Don Dingee on 04-04-2016 at 4:00 pm

In our previous post on SoC memory resource planning, we shared 4 goals for a solution: optimize utilization and QoS, balance traffic across consumers and channels, eliminate performance loss from ordering dependencies, and analyze and understand tradeoffs. Let’s look at details on how Sonics is achieving this.… Read More


4 goals of memory resource planning in SoCs

4 goals of memory resource planning in SoCs
by Don Dingee on 03-21-2016 at 4:00 pm

The classical problem every MBA student studies is manufacturing resource planning (MRP II). It quickly illustrates that at the system level, good throughput is not necessarily the result of combining fast individual tasks when shared bottlenecks and order dependency are involved. Modern SoC architecture, particularly … Read More


DDR stands for Don’t Do (Just) RTL

DDR stands for Don’t Do (Just) RTL
by Don Dingee on 06-16-2015 at 9:00 pm

In optimizing SoC design for performance, there is so much focus on how fast a CPU core is, or a GPU core, or peripherals, or even the efficiency of the chip-level interconnect. Most designers also understand selecting high performance memory at a cost sweet spot, and optimizing physical layout to clock it as fast as possible within… Read More


Optimize Your Interconnect & Design at System Level for Best Results

Optimize Your Interconnect & Design at System Level for Best Results
by Pawan Fangaria on 09-16-2014 at 7:00 am

As the SoC design size, complexity and functionality keeps on increasing with multiple IPs packed together and design time and time-to-market keeps on decreasing amid critical constraints on PPA, there is no other alternative than to do the design first-time-right not to miss the window of opportunity. And that could be possible… Read More


Improve Your Memory the Sonics Way

Improve Your Memory the Sonics Way
by Paul McLellan on 07-22-2014 at 7:00 am

There is never enough memory bandwidth. Well, occasionally there is but many SoCs have lots of blocks that communicate through memory, typically off-chip DRAM. In 2001 Sonics created their first solution to this problem with MemMax technology that was incorporated into their SonicsSX product. This has been used in over 100 designs… Read More


ISO 26262 driving away from mobile SoCs

ISO 26262 driving away from mobile SoCs
by Don Dingee on 02-13-2014 at 10:00 pm

Connected cars may be starting to resemble overgrown phones in many ways, but there are critical differences now leading processor teams in a different direction away from the ubiquitous mobile SoC architecture – in turn causing designers to reevaluate interconnect strategies.

The modern car has evolved into a microcontroller… Read More