How to Efficiently and Effectively Secure SoC Interfaces for Data Protection

How to Efficiently and Effectively Secure SoC Interfaces for Data Protection
by Kalar Rajendiran on 01-04-2023 at 6:00 am

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Before the advent of the digitized society and computer chips, things that needed protection were mostly hard assets such as jewelry, coins, real estate, etc. Administering security was simple and depended on strong guards who provided security through physical means. Then came the safety box services offered by financial … Read More


Integrating High Speed IP at 5nm

Integrating High Speed IP at 5nm
by Pavan Patel on 11-10-2022 at 6:00 am

Figure 1

Introduction:

The advancements in deep submicron technology and adding multiple functionalities to reduce costs combined with scaling existing operations means that SoC designs become ever more complex. The biggest driving factors to go below the 16nm process node are the decrease in power and the increase in performance … Read More


Sondrel explains the 10 steps to model and design a complex SoC

Sondrel explains the 10 steps to model and design a complex SoC
by Daniel Nenni on 03-02-2022 at 10:00 am

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Sondrel just released a position paper on how to model and design a complex ASIC. We have been following Sondrel for the past year and I have found their collateral to be excellent. Here is the position paper overview, a description of the new Sondrel modeling tool, the 10 steps, and of course a link to download the paper:

Overview
It… Read More


Perform Simulation-based compliance Tests for (LP)DDR

Perform Simulation-based compliance Tests for (LP)DDR
by Admin on 01-26-2022 at 1:47 pm

Part of Keysight’s ‘Simulating for High-Speed Digital Insights’ webinar series

November 15, 2022 | 10:00 AM PT / 1:00 PM ET

Moving to the latest memory standards introduces new compliance testing procedures. As design margins shrink, it becomes ever more important to quantify that your implementation… Read More


Analyzing Memory Bus to Meet with DDR Specifications

Analyzing Memory Bus to Meet with DDR Specifications
by Admin on 01-26-2022 at 1:42 pm

Part of Simulating for High-Speed Digital Insights series

April 14, 2022 | 10:00 AM PT / 1:00 PM ET

Due to ever increasing data demand, the speed grade for memory is now in the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along with… Read More


Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions

Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions
by Daniel Nenni on 07-29-2020 at 10:00 am

Globalfoundries AI Webinar Hiren Majmudar

I had the pleasure of spending time with Hiren Majmudar in preparation for the upcoming AI Accelerators webinar. As far as webinars go this will be one of the better ones we have done. Hiren has deep experience in both semiconductors and EDA during his lengthy career at Intel and now with a pure play foundry. He is intelligent, personable,… Read More


Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level
by Admin on 02-20-2020 at 10:53 am

Double data rate (DDR) synchronous dynamic random-access memory (SDRAM) is the common type of memory used as RAM for almost every modern processor. With DDR memory interface voltages decreasing, speeds increasing, and timing/power budgets being squeezed, design qualification using the latest memory interfaces is no small… Read More


High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory

High Performance Ecosystem for 14nm-FinFET ASICs with 2.5D Integrated HBM2 Memory
by Mitch Heins on 02-07-2018 at 10:00 am


High Bandwidth Memory (HBM) systems have been successfully used for some time now in the network switching and high-performance computing (HPC) spaces. Now, adding fuel to the HBM fire, there is another market that shares similar system requirements as HPC and that is Artificial Intelligence (AI), especially AI systems doing… Read More


16nm HBM Implementation Presentation Highlights CoWoS During TSMC’s OIP

16nm HBM Implementation Presentation Highlights CoWoS During TSMC’s OIP
by Tom Simon on 09-29-2016 at 12:00 pm

Once a year, during the TSMC’s Open Innovation Platform (OIP) Forum you can expect to see cutting edge technical achievements by TSMC and their partners. This year was no exception, with Open-Silicon presenting its accomplishments in implementing an HBM reference design in 16nm. It’s well understood that HBM offers huge benefits… Read More


Optimizing memory scheduling at integration-level

Optimizing memory scheduling at integration-level
by Don Dingee on 04-04-2016 at 4:00 pm

In our previous post on SoC memory resource planning, we shared 4 goals for a solution: optimize utilization and QoS, balance traffic across consumers and channels, eliminate performance loss from ordering dependencies, and analyze and understand tradeoffs. Let’s look at details on how Sonics is achieving this.… Read More