You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
IEEE San Francisco Bay Area Council - E-GRID
Wednesday, December 6, 2017
SFBA Electron Devices Society (EDS)
Subject: 10th MOS-AK Compact Modeling Workshop in the Silicon Valley
- frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulations, compact/SPICE...
This is the call for participation in the FOSDEM 2017 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 5 February 2017 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following...
LLVM Dev Conference
There will be a discussion at a BoF meeting on extending the IR (intermediate representation) to support parallel constructs at the LLVM developers conference in November. Currently LLVM and Gcc don't support the light-weight reactive threading model used by HDLs, so this is...
I thought I'd post this -
Tenzing Norgay Interoperability Achievement Award
- with the thought that I'd really like to award a "wooden spoon" to some people for setting EDA and interoperability back by years. My nomination on that front for 2011 would go to Gordon Vreugdenhil for his efforts...
Sonics is suing Arteris for patent infringement. I find this interesting partly because I worked at Sonics, and I was under the impression that Arteris used a packet-switching technology rather than a straight-up bus. So maybe someone who is up-to-date on Arteris can comment.
<script...
So apparently everyone loved the dysfunctional "interconnect" and "nettype" proposals -
[sv-dc] Mantis items approved
You can find the work record here -
0003398: User defined nets and resolution functions - EDA.org Mantis
0003724: Allow generic interconnect for "typeless" connections -...
Arturo's comments on the latest SV-CC OO proposal may be indicative of how unstable SystemVerilog really is.
Back at the start of the SV standardization process, I was hopeful that we were going to get some simple way of bridging between Verilog and C then C++/SystemC - I made some proposals...
One would have thought that the meaning of "wire" in Verilog was obvious, but apparently not. According to some folks from Mentor & Cadence the semantics of wire changed at some indeterminate point in time (in the history of SystemVerilog) to be those of VHDL, and in order to add new type...
One of the problems with developing simulators and other EDA tools is a lack of good benchmarks and industrial scale sample code. So I thought I'd start a thread for people to post links to any useful Verilog-AMS, Spice, Verilog, VHDL and related tool data (e.g. run times) that can be used by...
For anyone who missed it: there were a couple of verification talks by Oracle folk at DV Club this week. The first (Greg Smith) was pretty good, you can find his presentation here - Design Verification Club 2011 Speakers - the second I could have skipped, but was interesting in that the guys...
A friend of mine went to a presentation on Verilog-AMS (by Cadence) and was confused by how complicated it appeared to be. So I thought I'd post something on what the thinking behind it was.
The working assumption was that digital designers and verification engineers don't want to know about...
Gary McGraw gave one of the more interesting talks today at the Software Experts Summit on "The Building Security In Maturity Model".
It struck me that similar metrics could be applied to chip design and it might be possible to objectively track whose approach (companies or teams) to design...
I remember sitting through presentations a few years ago on Innologic's symbolic simulation tools, and it struck me as a very useful semi-formal method for verifying logic.
I wanted to try it on NoC testing since the conditions for correct behavior are fairly easy to identify (i.e. don't...
Here's a Cadence paper from 2002 - http://w2.cadence.com/whitepapers/4064_NanometerWP_fnlv2.pdf
Another from 2003 - In Nanometer IC Design, Accurate Wiring Details Hold The Key To Success
At a presentation about Calibre it was stated that 70% of capacitive load was wiring, but no mention was...
SystemC AMS Day 2011 - Open SystemC Initiative (OSCI)
SystemC-AMS and Design of Embedded Mixed-Signal Systems
Given the slow up-take of Verilog-AMS, I find it hard to believe that there are that many people actually using SystemC-AMS, and given the dysfunctional signal communication semantics...
An email to the SV committees yesterday -To all P1800 Technical Committees,
The Working Group has reviewed the new IEEE participation policies and has determined how they will affect the Working Group and the Technical Committees. Below is a summary of the new policies.
These changes take...
The DVcon panel session with the title above was well attended, and it looks like everybody is on board with UVM.
[ DVCon 2011 ]
An interesting lesson in how open-source can work in practice.
From my perspective this is good because UVM probably defines which parts of the SystemVerilog...
I've seen a lot of talk about "platform based design" in the last few years. As far as I can tell this mostly pushed by folks who have a platform to sell (e.g. ARM, TI, MIPS...). For me the "platform" is not a choice you would want to make at the start of the design process, but something to do...
