simguru
Member
The DVcon panel session with the title above was well attended, and it looks like everybody is on board with UVM.
[ DVCon 2011 ]
An interesting lesson in how open-source can work in practice.
From my perspective this is good because UVM probably defines which parts of the SystemVerilog standard you need to worry about implementing. I.e. the language is overly complex and has plenty of things you probably never want to use, so if you only implement enough to support UVM, that's probably good enough for the bulk of customers - a lowest common denominator.
As usual no mention from the panel of analog/mixed-signal verification until an audience member asked (not that there was a useful answer).
Anybody want a translator for converting it to C++?
[ DVCon 2011 ]
An interesting lesson in how open-source can work in practice.
From my perspective this is good because UVM probably defines which parts of the SystemVerilog standard you need to worry about implementing. I.e. the language is overly complex and has plenty of things you probably never want to use, so if you only implement enough to support UVM, that's probably good enough for the bulk of customers - a lowest common denominator.
As usual no mention from the panel of analog/mixed-signal verification until an audience member asked (not that there was a useful answer).
Anybody want a translator for converting it to C++?
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