simguru
Member
A friend of mine went to a presentation on Verilog-AMS (by Cadence) and was confused by how complicated it appeared to be. So I thought I'd post something on what the thinking behind it was.
The working assumption was that digital designers and verification engineers don't want to know about analog, and vice versa, so it would be best to make the interfaces between the digital and analog parts of the design a separate part of the language that could be handled by CAD engineers. My design goal was to allow mixing of standard digital cell descriptions with analog descriptions of wiring - anticipating wiring being the dominant delay effect, i.e. use SPEF instead of SDF. By typing the ports on the digital cell you could indicate which digital-to-analog (d2a) or analog-to-digital (a2d) simulation elements to use to bridge in and out of the SPEF. The contents of the d2a/a2d "connect" modules are just more Verilog-AMS rather than being built into the simulator so that the entire design is portable and could handle a wide variety of circuits.
For the analog modeling (in order to compete with VHDL/MAST etc.) the "discipline" type scheme was added so that you could say whether a wire represented an electrical connection or some other physical quantity (like fluids, or heat). We just overloaded that with a class hierarchy mechanism so you use it to indicate the a2d/d2a choice, the idea being that you could use the class hierarchy to refine attributes as you work down from the Silicon process to the particular library then the ports on a particular cell. The connection rules (for d2a/a2d insertion) are defined separately so that you can add more rules as the pieces of a design come together and you can modify accuracy to meet specific verification needs.
Creating a Verilog-AMS version of a digital library should be a fairly straight forward job for a CAD engineer. If you have an automatic test pattern generator and an optimizer, you just run an all-analog version of a test circuit against the mixed digital/analog version and tune the d2a/a2d parameters to get a good match, and then use the tuned parameters in the connection rules.
Unfortunately the simple SPEF back-annotation flow never got into the language, so Verilog-AMS has made little inroad as a digital verification language - if you want to use the language that way you would need to create the appropriate netlist yourself - another job for the CAD engineers.
The working assumption was that digital designers and verification engineers don't want to know about analog, and vice versa, so it would be best to make the interfaces between the digital and analog parts of the design a separate part of the language that could be handled by CAD engineers. My design goal was to allow mixing of standard digital cell descriptions with analog descriptions of wiring - anticipating wiring being the dominant delay effect, i.e. use SPEF instead of SDF. By typing the ports on the digital cell you could indicate which digital-to-analog (d2a) or analog-to-digital (a2d) simulation elements to use to bridge in and out of the SPEF. The contents of the d2a/a2d "connect" modules are just more Verilog-AMS rather than being built into the simulator so that the entire design is portable and could handle a wide variety of circuits.
For the analog modeling (in order to compete with VHDL/MAST etc.) the "discipline" type scheme was added so that you could say whether a wire represented an electrical connection or some other physical quantity (like fluids, or heat). We just overloaded that with a class hierarchy mechanism so you use it to indicate the a2d/d2a choice, the idea being that you could use the class hierarchy to refine attributes as you work down from the Silicon process to the particular library then the ports on a particular cell. The connection rules (for d2a/a2d insertion) are defined separately so that you can add more rules as the pieces of a design come together and you can modify accuracy to meet specific verification needs.
Creating a Verilog-AMS version of a digital library should be a fairly straight forward job for a CAD engineer. If you have an automatic test pattern generator and an optimizer, you just run an all-analog version of a test circuit against the mixed digital/analog version and tune the d2a/a2d parameters to get a good match, and then use the tuned parameters in the connection rules.
Unfortunately the simple SPEF back-annotation flow never got into the language, so Verilog-AMS has made little inroad as a digital verification language - if you want to use the language that way you would need to create the appropriate netlist yourself - another job for the CAD engineers.
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