SDF - past it's use-buy date?

[simguru]

Here's a Cadence paper from 2002 - http://w2.cadence.com/whitepapers/4064_NanometerWP_fnlv2.pdf

Another from 2003 - In Nanometer IC Design, Accurate Wiring Details Hold The Key To Success

At a presentation about Calibre it was stated that 70% of capacitive load was wiring, but no mention was made of differing path delays on multiple fan out, and there was a suggestion that the margin of error on extracting the wiring data was quite high - i.e. there is a spread that is not being considered in derived simulation models.

Is anybody still using Verilog + SDF for sign-off, and how do the results compare with Spice (and actual results)?

 

[Kiby]

We are a Cadence user and it is fun to compare documents from years or even months past. New people come into Cadence and it is like a new company. Then they leave and it is a new company again. EDA360 was presented to us last year and we have not heard another word about it since. What new company will Cadence be this year? I can't even read their website without laughing.

NEW CADENCE CUSTOM ANALOG DELIVERS A HOLISTIC APPROACH TO 20NM SILICON REALIZATION! Hahahahahaha!

But to answer your question we never used Verilog+SDF for sign-off. Always Spice which is closest to actual results all times. Now we use a fast Spice too.

Kiby!

 

[John Busco]

Here's a Cadence paper from 2002 - http://w2.cadence.com/whitepapers/4064_NanometerWP_fnlv2.pdf
At a presentation about Calibre it was stated that 70% of capacitive load was wiring, but no mention was made of differing path delays on multiple fan out, and there was a suggestion that the margin of error on extracting the wiring data was quite high - i.e. there is a spread that is not being considered in derived simulation models.

Is anybody still using Verilog + SDF for sign-off, and how do the results compare with Spice (and actual results)?

SDF has the INTERCONNECT construct to model RC delays, which is what I believe you refer to by "different path delays on multiple fanout". Each delay from a driving cell's output pin to a driven cell's input pin can have a different delay. Therefore, the delay accuracy can be comparable to Static Timing Analysis.

When you say "Verilog + SDF", are you referring to gate-level simulation? Designers don't usually rely on that because it's not exhaustive like STA is. They might spot check some special cases like reset or weird logic that doesn't look like normal synchronous logic to STA, but rely on STA for the vast majority of timing sign-off.