SystemVerilog development becomes "entity only"

[simguru]

An email to the SV committees yesterday -

To all P1800 Technical Committees,

The Working Group has reviewed the new IEEE participation policies and has determined how they will affect the Working Group and the Technical Committees. Below is a summary of the new policies.

These changes take effect immediately.

The aliases are in the process of being scrubbed. For now, we should continue to use the set of aliases that are currently in place. A new set of aliases will take effect when they are stabilized. Another email will be sent when we should be switching over to them.

Pages 9, 10, 11 of the following document describe the rules for Entity based standards. The P1800 is Entity based and will follow these rules.

http://standards.ieee.org/develop/policies/bylaws/sb_bylaws.pdf

In addition to the rules described in the IEEE-SA bylaws document the following rule is also in affect. Only employees of Entities that are voting members of the Working group will be allowed to participate in any of the Technical Committees. The Technical Committee chairs will need to start policing their meetings to ensure that only employees of the following companies are allowed to participate.

Cadence
Freescale
Intel
Marvel
Mentor
Oracle
Synopsys
Accellera (Designated Representatives, as opposed to employees)

Other companies may choose to become voting members of the Working Group. If this happens, employees of those companies will also be allowed to participate.

This is a big set of changes and there will be a noticeable impact on various committees. We will most likely have more questions as we start implementing them.​

 

[gmartin]

Curious, I went to the link to find the following on page 11 of the pdf:

11
5.2.1.4 Openness
Openness is defined as the quality of being not restricted to a particular type or category of participants. All meetings involving standards development shall be open to all interested parties.

So I wonder if a non-entity person is allowed to observe (silent participation) - i.e. attend and listen to the proceedings? Not allowing observation seems to contradict the Openness definition. But you can only effectively allow observation if you publicise the meetings and thus allow it. I could not see a definition of "participation" to imply that it means more than observation - i.e. the right to make a verbal or written comment? On p. 10 there is an indication that only Advanced Entity members of an Entity-based working group can "contribute" but I assume "contribute" means more than just making a comment. It is very clear as to voting rights etc. for entity-based standards groups.

I am not involved in SystemVerilog in any way, but am curious that the SV P1800 group seems to be "scrubbing the aliases" of the technical groups to remove non-Entity based individuals. Again, email aliases are presumably used for discussion and comment and for notice of upcoming meetings. Scrubbing the aliases of those who want to be observers and follow the discussion and listen in seems to contradict the Openness provision.

At one point I thought the IEEE standards procedures, even with the move to Entity-based standards, were reasonable at least from the point of transparency because individuals could observe (and maybe comment). This seems to be disappearing, unless I am misreading the actions above. I have not been involved in standards activities for a while (several years) but this seems to be moving too far. Buying votes is one thing (the Entity mechanism is definitely that) but it is not good to remove openness, and a contradiction it appears.

Just my personal point of view

 

[simguru]

Observer effect (physics) - Wikipedia, the free encyclopedia

Maybe some scrutiny will help

SystemVerilog Enhancement Committee: By Thread
SystemVerilog Discrete Real Modeling Committee: By Thread
System/Verilog Basic Committee: By Thread
Accellera SuperVerilog Assertion Activity: By Thread

 

[JimLewis]

5.2.1.4 Openness ...

Openness simply means that anyone can join, if they pay the fee. This is clarified in section 5 (html) if you keep reading.

So I wonder if a non-entity person is allowed to observe (silent participation) - i.e. attend and listen to the proceedings? Not allowing observation seems to contradict the Openness definition.

The rules allow you to attend one meeting as a non-member. Sending email on a working group reflector is participating. Reading a working group email reflector is observing. Hence the requirement to remove the RIF-RAF from the reflector, such as myself who has been observing.

Note that these rules were put in place in December of 2009, so the EDA community has already had 1+ years to clarify and/or object before DASC resolved to enforce the rules. In the DASC 2/14/2011 meeting minutes, the DASC issued the action item

Entity WG chairs should strike non-entity members from their email reflectors.

The fees for membership are here. Keep in mind that none of these fees come back to the working group. So to fund standards activities, a separate assessment is required. Note also that each working group is also permitted to charge a substantial per meeting fee, although I haven't heard of that happening within a DASC working group.

These rules really seem to be well suited for working groups developing a big dollar standard such as ethernet. They do not seem to be a great match for EDA standards where both vendors and users particpate. For a user company, the design and verification lanaguages are only one or two tools among many in the flow of developing a product. The Accellera rules seem to be a better match for EDA standards, where all can participate, however, when there is a contentious decision, the members have the final say.

I had to look into these rules since the VHDL WG was getting a push from some EDA vendors to be an entity based group. Some representatives from EDA companies have expressed the opinion that a working group is not relevant unless it is entity based. Curious, now that SystemVerilog has decided to follow the rules, it only has four members who are not EDA companies: Freescale, Intel, Marvell, and Oracle. Is that even a relevant representation of the companies who use SystemVerilog? Yikes.

I hope Accellera has read the IEEE rules, because if they don't fund participation (such as travel) for their representatives, then by the following, the person is instead representing the company or individual who funds their participation and is not a member of the WG unless they have joined as an entity member themselves:

5.2.1.5 Disclosure of Affiliation
Every member and participant in a working group, Sponsor ballot, or other standards development activity shall disclose his or her affiliation. An individual is deemed "affiliated" with any individual or entity that has been, or will be, financially or materially supporting that individual's participation in a particular IEEE standards activity.

 

[gmartin]

Jim

Thanks for the further discussion. As I mentioned, I haven't been following much standards stuff for a while, but I have a blog reader that picked up the original posting and I got interested. I also tried to find further in the html link for section 5 where it really defines what an "interested party" is, and whether they must pay fees, and also what "All meetings involving standards development shall be open to all interested parties." really meant, but I couldn't find a definition that closes the loop on that. Maybe if you find the relevant section you could cite the particulars specifically.

However, if you can't be on the email reflector (to read the activity; heaven forbid that an observer dare to post a comment! Hey, it might be a good one and influence someone), then it is difficult to see how that is open by the definition, since so much business is carried on by email discussions, as well as in meetings. And if the notice of a meeting only gets on the reflector and all non-members are pruned off it, then there is a catch-22 somewhere here.

I still think this is a bit of a shame, and it pulls the credibility of the IEEE standards process down a few notches. Transparency and openness are good for standards, and occasionally even an "unpaid-for" comment might be worth listening to. As I mentioned, in some ways the old rules seemed a good compromise between corporate desires for control (which entity based membership allows via voting rights etc.) and the desire by others to follow what is going on.

But pay for play seems to be the way much of the world is going........

 

[JimLewis]

But pay for play seems to be the way much of the world is going........

I like calling it the gold standard - those with the gold get to play

It does not have to be this way though. e, VHDL, and VHDL-AMS are all individual based working groups which allow any interested party or anyone with a vested interest (this is how they said it in the past and is my preferred wording) to participate. The tricky part then is determining how to fund standards editing, which in the case of VHDL is significant.

IEEE-SA has lots of challenges. Some time in the late 90's they were spun out as a separate organization. I don't have enough of an accounting background to really understand the financial reports, but it looks to me like social organizations such as the local chapters, and if you are in the USA, IEEE-USA, get significant funding directly from your IEEE dues, however, the professional standards organization, IEEE-SA, gets nothing directly - instead they only get what they collect as IEEE-SA dues.

I find this offensive, however, I have not found the right forum to present it. I suspect that if IEEE-SA received what either IEEE-USA or a local chapter receives, then IEEE standards could probably be more like open standards and freely available. I suspect one of IEEE-SA's interest in corporate standards is a reliable yearly revenue source.

Maybe you can read the financial reports better than me and would have a good forum to present it? I don't mind handing off the torch to anyone willing to run with it.

Transparency and openness are good for standards, and occasionally even an "unpaid-for" comment might be worth listening to.

This is too bad for SystemVerilog as they are going to loose a number of valuable contributors. I suspect they will try to sneak some of them in as Accellera representatives, however, that is an ethical issue as I doubt in real life that any of these people ever sell their services for free, and hence, Accellera would neither be financially nor materially supporting them.

In the VHDL process we have found individual contributions to be highly valuable and this is why VHDL is individual based. Who wants to turn down free work?

See the DASC meeting minutes from 2/14 for clarifications of how DASC interprets the corporate rules.