What Hot Chips 2026 Tells Us About What Silicon Valley Is Actually Building

Here’s what the presentations selected for the 2026 Hot Chips Conference tell us about what Silicon Valley companies are doing these days.

The conference, running this week at Stanford’s Memorial Auditorium, doesn’t publish detailed abstracts ahead of time, but the program itself, just the lineup of who’s presenting what, is a legible snapshot of where the industry’s attention has actually gone in 2026. A few patterns stand out.

Memory is the story, and everyone’s solving it the same way. A full tutorial block plus a dedicated conference-day session is devoted to memory: Micron, Samsung, SK Hynix, D-Matrix and Meta, Oxmiq Labs, and more. But look closely at the titles and a pattern emerges: every single one of them is optimizing around the existing DRAM cell, not replacing it. HBM base dies on advanced logic processes.

Advanced packaging for HBM: 3D-stacked DRAM accelerators and Processing-in-memory add-ons. Nobody on this program is proposing to reimagine the memory cell itself: the one-transistor, one-capacitor structure that’s defined DRAM since 1966. The entire industry’s best minds are, by their own programming choices, telling us the consensus path forward is better packaging, not a better cell.

RISC-V has graduated from promising to mainstream. The tutorial track alone spans standards and platform convergence: SiFive, Canonical, NVIDIA GPU interoperability, and automotive deployment, Infineon. These give evidence that RISC-V is no longer a niche architecture bet but a genuine cross-industry standard being built into everything from enterprise Linux stacks to cars.

RVA23 and Ubuntu 26.04’s support for it are real steps toward eliminating the current patchwork of vendor-specific kernel forks — but true out-of-the-box compatibility isn’t an accomplished fact yet. Jefro Osier-Mixon of Red Hat has acknowledged that most RISC-V vendors today are still running their own out-of-tree kernel forks loaded with custom patches, some built on kernels years out of date and carrying hundreds of drivers that never made it into the mainline Linux codebase. That’s the gap RVA23 and efforts like Ubuntu’s are meant to close — but as Red Hat’s own account of the current state makes clear, most RISC-V deployments still require custom patching today.

The GPU race has become a sprint. NVIDIA is showing Rubin GPU and its new Vera CPU. AMD has two separate talks on its Instinct MI400 series. Intel is presenting Crescent Island, explicitly framed for “agentic AI inference.” That’s three of the industry’s biggest silicon players putting their newest architecture, unfiltered, on the same stage in the same week. This level of competitive transparency is becoming the norm rather than the exception.

Look closer at the memory choices behind those three chips and a real divide emerges. NVIDIA’s Rubin and AMD’s Instinct MI455X both lean on HBM4 for their accelerator memory—288GB and 432GB respectively, with NVIDIA delivering roughly 22 TB/s of bandwidth and AMD’s chip close behind at 19.6 TB/s. Intel’s Crescent Island goes the other way, built around LPDDR5X instead of HBM, a different bet entirely. HBM offers dramatically higher bandwidth but costs far more per gigabyte and sits squarely at the center of the current supply shortage everyone’s discussing.

Intel is explicitly trading raw bandwidth for capacity, cost, and power efficiency, betting that for many inference workloads, especially ones bottlenecked by needing to hold a large model resident rather than needing maximum bandwidth, that tradeoff wins on total cost of ownership, particularly in air-cooled enterprise servers rather than hyperscale liquid-cooled racks. NVIDIA wins bandwidth, AMD wins capacity, Intel wins cost/power/availability. Each is choosing a different axis to lead on rather than all competing head-on for the same crown.

Autonomous driving has arrived as a mainstage topic, not a sideshow. Waymo delivers the Tuesday keynote and co-presents in a dedicated automotive session alongside BOS Semiconductors. Self-driving compute is no longer a specialty track; it’s central programming.

AI labs designing their own chip, not buying from chip vendors. OpenAI’s talk, bluntly titled “You Can Just Build Things … Chips.” Paired with Google’s eighth-generation TPU talk and Meta’s custom silicon presentation, it marks a real structural shift. The companies that used to simply buy compute from NVIDIA and AMD are now standing on the same stage as silicon designers in their own right.

Put together, the 2026 program reads less like a list of individual product announcements and more like a referendum on where the industry believes the real constraints sit right now: not in raw compute, but in memory bandwidth, in open-standard flexibility, and in who controls the silicon roadmap for AI itself. What’s largely absent — a genuine architectural rethink of the memory cell — may turn out to be the more interesting story once someone finally puts it on the agenda.

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