- This event has passed.
What’s the Recipe for Efficient Analog IC Design and Verification?
May 19, 2021
For analog IC designers, the most important capability is rapid simulation of an accurate model of their circuits. Early in the design process, they explore architectures and novel approaches and need an agile simulation flow that gives them confidence that the implemented design is capable of meeting the system specs. As the design matures, the focus changes to comprehensive and transparent verification of circuit performance, reliability, yield, and functionality within the context of a larger system.
The Cadence® Virtuoso® ADE Product Suite including Virtuoso ADE Assembler and Virtuoso ADE Verifier together with the Spectre® circuit simulator deliver a tightly integrated flow, which is an unrivalled partner for both design and verification. Backed by the industry’s leading R&D and Application teams, the Virtuoso ADE Product Suite enables easy re-use of both circuit and testbench IP.
In this CadenceTECHTALK, we will showcase the latest features of the Virtuoso ADE Product Suite:
- Variation-driven design using Monte Carlo analysis Creation and validation of block behavioral models
- Partial and full post-layout flow improvements
- Analog regression and coverage flows
- Signoff checks
Date and Time
Wednesday, May 19
9:00 BST / 10:00 CEST / 11:00 EEST and IDT / 13:30 IST