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Shrink is rapidly coming to an end and what changes in architecture and software will be the next frontiers to replace it? Will it be larger chips or ways of offloading functions to other adjoining chips? Will communications improve to the point that the next area of competition will be in the data center and the communications required? Will memory and how it is handled be part of the solutions? Any thoughts on how this will be done and what companies will bring out new business and technical models for meeting the coming challenges?
They can continue to increase chip complexity vertically. Making increasingly taller transistors. Stacking wafers on top of each other.
Cooling then becomes an issue. Clockspeeds might go massively down to decrease heat, or you will see larger chips, to increase the dissipation area.
Another alternative is switching from silicon to materials which dissipate heat better like diamond.
Shrink is rapidly coming to an end and what changes in architecture and software will be the next frontiers to replace it? Will it be larger chips or ways of offloading functions to other adjoining chips? Will communications improve to the point that the next area of competition will be in the data center and the communications required? Will memory and how it is handled be part of the solutions? Any thoughts on how this will be done and what companies will bring out new business and technical models for meeting the coming challenges?
Shrink is rapidly coming to an end and what changes in architecture and software will be the next frontiers to replace it? Will it be larger chips or ways of offloading functions to other adjoining chips? Will communications improve to the point that the next area of competition will be in the data center and the communications required? Will memory and how it is handled be part of the solutions? Any thoughts on how this will be done and what companies will bring out new business and technical models for meeting the coming challenges?
Nothing will replace the previous transistor growth that we once enjoyed that is associated with the term of moors law. Instead we will witness incremental improvements in transistor architecture (CFET, VFET), design technology co-optimisation (buried power rails, super bias, back of the line transistors), optical interconnections and vertical integrated packaging that will be introduced in waves over the next several decades that will lead to an incremental increase in density.
Even though it won’t replace the standard exponential speed in transistor growth, I still expect a performance and energy improvement of between fifty to hundred over the next twenty six years.
Dennard scaling ended in 2005 ish with a 1nm gate ox. Continued scaling was enabled by advanced materials and overlay and cd control scaling. Overlay control scaling in 3d will continue to enable rapid energy per floating point operation reduction. 1aJ/flop will likely enable a singularity defining computer at or about 2045 when we can get 3d overlay thru stack to 1nm. Advanced materials in device and interconnect clearly required
Let's not forget that we used to spend 2-3 years or more on a new process technology before releasing it to HVM and now we deliver them every year. At the mid point we used to do optical shrinks for high volume customers but those are not mentioned. Notice that TSMC does not count 6nm and 4nm as separate nodes. The big gap between .13m and 90nm was a huge debacle with copper interconnects. The gap between 40nm and 28nm was High-K Metal-gate technology, a debacle also for those who chose gate-last (GF, Samsung, IBM, etc....) while Intel and TSMC chose gate-first. TSMC 20nm and 10nm were skipped nodes. I think Apple was the only ones in HVM for those two. Same thing for 7+nm which was 7nm with some EUV layers and 6nm with more proper EUV. TSMC was definitely less risk adverse before Apple came to town at 20nm.
People forget that Moore’s Law was about doubling the number of transistors which for many decades was about scaling and shrinking. The naive and uneducated assumed if lithography or other things like the size of atoms would limit and slow it down.
What it is, Moore’s law is an Economic Law where if you roughly double the computational capability at the same price than amazing things happen. As noted for decades it was about shrinking gate lengths, CPP, and metal pitches. Then came material and structural tricks and now we have desegregated dies and CoWAs. In the end the business driving this is multi trillion so the motivation to provide new innovation is huge.
The naive get bogged down in the fact transistors aren’t scaling or energy isn’t scaling. All that the business needs to do is enable the end users to double their computational capability every so many years. Actually if you look at AI metrics they are doubling far faster than the underlying silicon technology.
Someone said exponential growth can’t continue forever, they discounted the ingenuity, greed, and desperation of humans.
I remembered reading about the end of scaling before I entered the industry at 1um. Also remembered the questions of many new recent graduating students and new young employees worried if they could retire in this industry.
To quote Mark Twain “The reports of my death are greatly exaggerated!!
Shrink has not completely ended, but let's just postulate 14A is the end of the line for logic, including SRAM. Channel length cannot get any shorter, spacing between devices cannot be narrower, and CFET actually works.
But there are still things that keep changing. DRAM has yet to go true 3D. It will happen, or something better will replace it. The DRAM is typically more silicon in your device than the logic, so that will be very significant.
Manufacturing costs will keep declining. If the nodes do not get smaller but there is still competition (the current flurry of new fabs might actually turn it into a buyers' market) then there are two things vendors will do: lower costs, and improve quality. Both will be possible. Cutting edge machines will become routine and less fragile. 2.5D and even 3D assembly will exceed 95% yields. Uniformity will increase, defectivity decrease, materials will be refined. Power consumption will continue to drop, slowly. Chiplets and better yields will mean sophisticated devices are cheaper.
As costs decline, memory grows, and production increases we will anable endless creativity with A14 densities. The industry will not stop growing, if it unlocks that creativity. Starting now, this means finding a revolution in access to EDA available to everyone with an idea. Like software did 40 years ago, dragging hardware into the future. It is the closed world of EDA which is more likely to derail the industry than the process technology. Imagine the software we would (not) have today if software had remained in the domain of the mainframe priesthood, or even the mini acolytes. That is what hardware design feels like today, like the liberation of creativity never happened.
