Webinar: Auto-generation of Verification Infrastructure for IP to SoC
Webinar: Auto-generation of Verification Infrastructure for IP to SoC
DVClub Europe Meeting –November 2023 Agenda (BST): 12.00 GMT - Welcome and Introduction Mike Bartley,Tessolve 12.00 GMT - Saving Development Time by Automating Verification infra from specifications Anupam Bakshi, Agnisys 12.30 GMT - Generation of Functional Coverage for RISC-V Processor Verification Larry Lapides, Imperas Software Ltd. 12.45 GMT - Breker 13.00 GMT - Close About …
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