Webinar: Removing the Risk from RISC-V using the RISC-V Trace Standard

With the growing maturity of the RISC-V ISA, chip companies now have a wealth of options for implementing RISC-V cores in their latest product. At the same time the support ecosystem is growing, with standards now defined for support technologies such as processor trace, which gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems based on a new ISA. In this presentation Siemens, as a lead technical contributor to the trace spec, will give an overview of how processor trace is used to improve embedded software and applications, what is contained in the trace specification, and a description of the Enhanced Trace Encoder from Tessent Embedded Analytics, the market-leading trace solution for RISC-V and the only commercial IP that is designed to meet the official RISC-V trace specification

Who should attend:

• SoC Architects
• Software Architects
• Embedded Software Engineers
• Anyone considering or already using RISC-V

What you will learn:

• We will examine the RISC-V trace standard and show how it reduces some of the risks of adopting RISC-V
• We will see how the non-intrusive visibility which it provides can be used to understand program behavior for advanced debugging and code optimization
• We will also examine suitability for the high-complexity heterogenous chip era by comparing the efficiency of this new standard against older methods