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CadenceTECHTALK: Cadence Certus | Delivering Overnight Concurrent Full-chip Optimization and Signoff

February 17 @ 2:00 PM - 3:00 PM

Date: 2023 .02. 17 (Thursday)

Time: 14:00pm – 15:00pm (Taipei Time)

Wondering how to accelerate your design closure?

The Cadence Certus Closure Solution is the industry’s first fully automated and massively distributed environment for full-chip optimization and signoff. It delivers up to 10X concurrent chip-level optimization and signoff. Furthermore, it supports the high-capacity requirements of modern designs with the unlimited capacity of placeable instances. It employs a new architecture based on massive parallelism to support true, fully automated, and massively distributed hierarchical optimization and signoff closure for the full chip.

Registration for Cadence Certus webinar is now OPEN!

Welcome to join us and learn more about this exciting new product.

Webinar will be delivered in Mandarin!

Speaker

Jason Huang, Cadence

REGISTER HERE

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