Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than the equivalent RTL simulations. Additionally, GLS bring-up and debug is slow and manual. In GLS, engineers spend time cleaning up sources of unknowns (Xs).  Xs can be caused by uninitialized inputs, registers, and simulation artifacts such as X-pessimism. Ad-hoc methods to handle Xs in GLS could mask problems.

This webinar will describe a reliable formal-based method to manage Xs in GLS.  It centers on the use of Siemens Avery SimXACT solution alongside your preferred simulator.

What You Will Learn: 

• X mitigation techniques to use in RTL
• How to eliminate X-pessimism in GLS for a streamlined bring-up
• Generate fixes for unknowns in a fraction of time compared to manual debug
• The SimXACT workflow

Who Should Attend: 

• Designers and Design Verification engineers
• Design Managers and Directors responsible for project tapeout schedule

What/Which Products are Covered:  

• Siemens Avery SimXACT
• Questa simulation