Loading Events

« All Events

  • This event has passed.

Stratus HLS (High Level Synthesis) Seminar Series: [Part 5] Verification of high-level synthesis RTL and Stratus integration flow

November 10, 2023 @ 3:00 PM - 4:00 PM

Screenshot 2023 10 04 051117

Date and time: Friday, November 10, 2023 15:00-16:00

Sponsor: Japan Cadence Design Systems, Innotek Co., Ltd. IC Solution Headquarters

Cost: Free

Venue: Online (Zoom webinar)

*You can also participate from a web browser.

We recommend using Google Chrome, Firefox, or Chromium Edge.

Registration deadline: November 9th (Thursday) 16:00

[Event overview]

In recent years, as LSI designs become larger and more complex, many developers are seeking greater design efficiency and are moving to more abstract design environments.

Since its release, Cadence’s high-level design and verification environment solution Stratus High-Level Synthesis (HLS) has been used by many customers around the world.

This time, we will be holding a webinar series to explain the basics of high-level design, implementation in RTL, and solutions related to its verification.

A total of 5 webinars will cover topics such as the basics of high-level synthesis, SystemC, how to use high-level synthesis, and verification after RTL synthesis.

For those who are interested in high-level design, those who are considering introducing high-level design, and those who want to increase their knowledge, this is a good opportunity to learn what HLS is.
Please join us for this webinar series.


Share this post via: