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Timing Closure Techniques for SOCs with Embedded FPGA Fabric

Timing Closure Techniques for SOCs with Embedded FPGA Fabric
by Tom Simon on 08-07-2018 at 12:00 pm

Once the benefits of using an embedded FPGA fabric are understood, the next question is about how timing closure is handled between the ASIC and the eFPGA blocks. First let’s look briefly at the advantages. By moving the eFPGA on to the SOC die, tons of I/O logic and the need for any package and board interconnect will vanish. Package and board routing create messy signal integrity and timing issues that require SerDes and bus protocols to tame. The added benefits also include reduced power – less logic to drive – and much lower latency. Instead of using a pair of SerDes, now the ASIC and eFPGA talk over direct wired signal nets.


While talking to Volkan Oktem, Achronix’s Senior Director of Product Applications, about the topic of timing closure with eFPGA I learned that there are two approaches for connecting the eFPGA to signals on the ASIC side. The easiest way is to use what they call “simple timing mode”, where there is a register on each net to help timing handoff at the eFPGA boundary. Of course, if you want to have the eFPGA output a signal off-chip, the SOC can include any necessary interfaces. But, the eFPGA can be thought of as just more logic – that just happens to be programmable.


In simple timing mode, the eFPGA and ASIC regions can be timed independently of each other. Constraints can be used in the eFPGA synthesis to ensure external timing meets spec. Then the ASIC just sees the eFPGA as a well-behaved block on the chip, like any other. For simulation, there is a gate level netlist with timing back annotation for the eFPGA so that top level timing can be verified.


If designers want to get rid of the extra clock cycle delay required by the intermediary registers, they can use the “advanced timing mode” which allows a direct connection from the ASIC logic to the input or outputs in the eFPGA. The catch is that the timing on these paths is now shared between the ASIC and the eFPGA. Achronix supplies a methodology that facilitates timing closure when using the advanced timing mode. First the user performs STA on the entire design, including the ASIC logic and the eFPGA logic. Next Achronix supplied scripts are used to extract the ASIC and eFPGA portions of all the nets that cross the boundary between the two parts of the design. Then these delays are passed as constraints to the ACE eFPGA tools so the eFPGA can be synthesized to meet timing. If there is more than one application for the eFPGA this process can be repeated for each.

After an iteration of the above process, designers can see if timing it met. If not, additional optimization or clock period adjustments can be made to close timing. While there is more effort required to use the advanced timing mode, it may well be worth it. Adding an eFPGA block to the floorplan otherwise is not much different than adding any other IP block. There are a few caveats, such as through routing is not allowed. So, placement of the eFPGA should take in to consideration the top level ASIC routing needs. There are no special supply or clock requirements.

An interesting side-note that came up in my conversation with Volkan was that for debug and test it is possible to program part of the eFPGA with special testers and debugging aids. This can help improve testability and visibility for the eFPGA and also the surrounding ASIC logic.

Volkan also pointed out that for some customers the goal is just to make a portion of an SOC programmable, adding for instance the flexibility being able to make post silicon logic changes. This affords the ability to refine and adapt functionality much later in the development process. However, he explained that sometimes their customer’s goal is to create special a purpose FPGA device, one that is tailor made for a specific application. This can have a number of advantages over off the shelf FPGA parts.

With a straightforward integration process, either with interface registers or through direct connection, the addition of programmability to an SOC design can be tremendously beneficial compared to off chip FPGAs or going without programmability altogether. Volkan has been working on developing new tools and documentation to make this process easy and efficient. There are resources on the Achronix website that go into much more detail and further explain clocking options and the timing closure process.