Intel Invests in the Fabless Ecosystem!

During my illustrious career one of the most useful axioms that I use just about everyday day is: “Understand what people say but also understand why they are saying it.” This certainly applies to press releases so let’s take a look at what Intel unleashed during #51DAC (in alphabetical order):

ANSYS And Intel Collaborate To Deliver Power, EM And Reliability Sign-Off Reference Flow For Customers Of Intel Custom Foundry –

Cadence and Intel Collaborate to Enable a 14nm Tri-gate Design Platform for Customers of Intel Custom Foundry –

Mentor Graphics Tools Fully Enabled on Intel’s 14nm Processes for Customers of Intel Custom Foundry –

Synopsys and Intel Collaborate to Enable 14-nm Tri-Gate Design Platform for Use by Customers of Intel Custom Foundry–

Building a fabless design ecosystem is a very difficult thing. TSMC has been doing it for 25 years which resulted in the Grand Alliance we have today. As the #1 pure-play foundry, ecosystem partners swarm TSMC. The big challenge is silicon validation which is what the TSMC OIP is all about. As the #1 consumer of EDA tools, Intel has a distinct advantage since they write some very big checks. Close to half a billion dollars a year I am told. Samsung is in a similar position, being one of ARM’s biggest customers Samsung foundry definitely has the IP advantage. Samsung also writes some very big partner checks.

When GlobalFoundries got started, they wrote some really big checks to EDA and IP vendors as well. In fact, they were some of the largest single orders for partners I have seen. If I remember correctly Virage Logic got $6M, all for the greater good of the fabless semiconductor ecosystem, absolutely.

Big ecosystem checks do not necessarily mean big wafer orders though so we will have to wait and see. It certainly is a step in the right direction and it tells me that Intel will be back for 10nm foundry business, even more agressivley than 14nm. The 10nm ecosystem press releases will be coming next. It’s a four horse race so let’s see who wins the 10nm PR derby.

I also think it is interesting to see the embedded quotes. Since these four press releases came out within minutes of each other it makes speculating even more fun.

“A close collaboration between Intel Custom Foundry and ANSYS on reliability verification reference flow for 22nm and 14nm enables our customers to efficiently deliver more robust and reliable designs for next-generation electronic products,” said Venkat Immaneni, senior director, Foundry Design Kit Enablement, Intel Custom Foundry. “This platform enables our customers to use an industry-leading power, EM and reliability sign-off solution on our design platforms.”

“Our collaboration with Cadence on tools and low power memory interface IP will allow our customers to take advantage of Intel’s 14nm design platform and design differentiated products for their markets,” said Ali Farhang, vice president, Design and Enablement Services, Intel Custom Foundry. “We are working together to ensure joint success of our customers.”

“We are very happy to be working with Mentor Graphics to ensure that a full suite of simulation and verification solutions are in place and optimized for our 14nm processes,” said Venkat Immaneni, Senior Director of Foundry Design Kit Enablement at Intel Custom Foundry. “This means our mutual customers can use the tools they have in place and are comfortable with, while taking advantage of Intel’s process leadership.”

“The combination of Intel’s 14-nm Tri-Gate process technology and Synopsys tools, memory and interface IP enables designers to create industry-leading SoCs for their target markets,” said Ali Farhang, vice president, Design and Enablement Services, Intel Custom Foundry. “By building on our successful collaboration on Intel’s 22-nm design platform, we have been able to seamlessly extend the solution to our 14-nm process technology.”

Before I give my expert speculation of the quotes maybe you can offer yours?

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