ESD Protection Network Checking is Difficult But Necessary

I’ve written before about anti-fuse non-volatile memory, where the gate oxide is intentionally damaged in order to create a readable bit of data, but this is what most circuit designers never want to have happen to their logic gates. However, since the advent of MOS transistors the issue of Electrostatic Discharge (ESD) and the resulting damage from voltage induced currents has been a key reliability issue. While it is possible to reduce the likelihood of an ESD event though proper handling and environmental controls, it is not possible to completely prevent them. An ESD event can cause excessive current that can damage or vaporize wires and vias, it can melt p-n junctions, and of course it can damage gate oxide.

The world of ESD is a world of things out of the normal. Circuit designers like it when transistors and interconnect are behaving linearly. There is nothing linear about ESD. Understanding and preventing ESD events and the resulting damage takes us into a world where everything is operating at extremes.

Shunting damaging currents caused by high electric potential is done by protection circuity in the pad ring. The protected devices in the core should never see high voltages or currents. It is the behavior of the ESD protection network that determines how the chip will fare. While the protection network is made of devices that are familiar, they are operating in modes that cannot be easily simulated using traditional circuit simulation methods.

There are a number of commercial solutions for analyzing ESD protection networks. Magwel is a company that started out developing field solvers for modeling transistors, but at the behest of several customers has developed a comprehensive ESD analysis solution called ESDi. I have been learning about Magwel and ESDi because I am working with them on several projects.

Magwel’s ESDi has a number of notable advantages over the previously existing tools. For one, ESDi can identify triggering of parasitic Bipolar junctions in MOS devices. It does this as it extracts the ESD protection network in the layout. These devices can be pre-characterized by the TCAD group and table models can be used to predict their behavior as part of the ESDi tool run. The same goes for the parasitic junction diodes formed in the MOS devices. This allows for proper modeling of avalanche and snap back behavior during ESD events.

Another key analysis capability of ESDI is that it models triggering of multiple protection devices, and can allocate the current among the various paths available. ESDi can do this because it uses extracted network resistance to calculate voltages at all the device pins. ESDi has a sequential algorithm that then allows for multiple devices to trigger. This avoids pessimistic current predictions, eliminating extra downstream work fixing problems that do not exist. It also can report electro-migration violations and high current densities along discharge paths.

Another advantage of ESDi is that it goes beyond what electrical rule checkers (ERC) do in determining if there is an adequate current limiting resistor in the discharge path. Rule checkers can tell you if you missed a resistor, but it cannot check to see if it has the correct value.

Magwel’s ESDi has many other unique features that make it extremely fast and accurate. Magwel will be at DAC in June this year in San Francisco. You will see their booth right as you enter the exhibit hall. Please contact them at sales@magwel.com for a demo at DAC or just drop by to learn more about ESD protection network verification. Magwel also has tools that address power transistor switching analysis, and thermally adjusted spice modeling for transistors.