Advanced Static Sign-Off Methodologies
Leading SoC designers will share their advanced static sign-off methodologies and best practices to support first-silicon design goals, along with results achieved in accelerating early functional verification and sign-off of digital designs.
Topics will include: AI/ML, targeted
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Event Information: Linear Static Model Setup (Solver Control Cards, Materials and Properties, Load Steps, Export Solver Deck or Run OptiStruct
Date and time:
Thursday, July 28, 2022 12:00 pm
Eastern Daylight Time (New York, GMT-04:00)
Program: Altair HyperWorks and Aerospace Coffee Breaks
Panelist(s) Info: Blaise Cole
Duration:… Read More
I am sure there are many FPGA designers who are quite content to rely on hardware vendor tools to define, check, implement and burn their FPGAs, and who prefer to test in-system to validate functionality. But that approach is unlikely to work when you’re building on the big SoC platforms – Zynq, Arria and even the big non-SoC devices.… Read More
Synopsys hosted a tutorial on verification for low power design at DVCon this year, including speakers from Samsung, Broadcom, Intel and Synopsys. Verification for low power is a complex and many-faceted topic so this was a very useful update. There is a vast abundance of information in the slides which I can’t hope to summarize… Read More
I’ve written before about anti-fuse non-volatile memory, where the gate oxide is intentionally damaged in order to create a readable bit of data, but this is what most circuit designers never want to have happen to their logic gates. However, since the advent of MOS transistors the issue of Electrostatic Discharge (ESD) and the… Read More
Synopsys announced verification compiler a couple of months ago and dropped hints about their static and formal verification. They haven’t announced anything much for a couple of years and it turns out that the reason was that they decided that the technology that they had, some internally developed and some acquired, … Read More
