Tag: static

CadenceTECHTALK: Static Timing Analysis and Some Important Basics

CadenceTECHTALK: Static Timing Analysis and Some Important Basics
by Admin on 01-16-2023 at 2:11 pm

Date: Thursday, January 26, 2023

Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST

Static Timing Analysis (STA) aims to validate the timing performance of a synchronous design. While it is a well-known concept in modern digital implementation flows, for engineers who are not familiar with STA or others who would like

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Altair HyperWorks and Aerospace Coffee Breaks: Linear Static Model Setup

Altair HyperWorks and Aerospace Coffee Breaks: Linear Static Model Setup
by Admin on 07-08-2022 at 2:32 pm

Event Information: Linear Static Model Setup (Solver Control Cards, Materials and Properties, Load Steps, Export Solver Deck or Run OptiStruct

Date and time:
Thursday, July 28, 2022 12:00 pm
Eastern Daylight Time (New York, GMT-04:00)

Program: Altair HyperWorks and Aerospace Coffee Breaks

Panelist(s) Info: Blaise Cole

Duration:… Read More

CadenceTECHTALK: Static and Dynamic IR Drop Analysis for Thermal Integrity of High-Performance PCB Designs

CadenceTECHTALK: Static and Dynamic IR Drop Analysis for Thermal Integrity of High-Performance PCB Designs
by Admin on 06-01-2022 at 3:00 pm

 

As boards become smaller and faster, the environment for thermal issues becomes increasingly challenging. The thermal management of significant resistive losses in PCB and package structures is critical, especially because these resistive losses are also temperature-dependent, making dynamic and static IR drop

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When FPGA Design Looks More Like ASIC Design

When FPGA Design Looks More Like ASIC Design
by Bernard Murphy on 06-08-2018 at 7:00 am
Categories: EDA, FPGA, Synopsys

I am sure there are many FPGA designers who are quite content to rely on hardware vendor tools to define, check, implement and burn their FPGAs, and who prefer to test in-system to validate functionality. But that approach is unlikely to work when you’re building on the big SoC platforms – Zynq, Arria and even the big non-SoC devices.… Read More

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Recipes for Low Power Verification

Recipes for Low Power Verification
by Bernard Murphy on 03-20-2017 at 7:00 am
Categories: EDA, Synopsys

Synopsys hosted a tutorial on verification for low power design at DVCon this year, including speakers from Samsung, Broadcom, Intel and Synopsys. Verification for low power is a complex and many-faceted topic so this was a very useful update. There is a vast abundance of information in the slides which I can’t hope to summarize… Read More

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ESD Protection Network Checking is Difficult But Necessary

ESD Protection Network Checking is Difficult But Necessary
by Tom Simon on 06-06-2015 at 6:00 pm
Categories: EDA, Magwel

I’ve written before about anti-fuse non-volatile memory, where the gate oxide is intentionally damaged in order to create a readable bit of data, but this is what most circuit designers never want to have happen to their logic gates. However, since the advent of MOS transistors the issue of Electrostatic Discharge (ESD) and the… Read More

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Synopsys Revamps Formal at #51DAC

Synopsys Revamps Formal at #51DAC
by Paul McLellan on 06-30-2014 at 6:02 pm
Categories: EDA, Synopsys

Synopsys announced verification compiler a couple of months ago and dropped hints about their static and formal verification. They haven’t announced anything much for a couple of years and it turns out that the reason was that they decided that the technology that they had, some internally developed and some acquired, … Read More