Power transistors are commonly used in applications like: hybrid vehicles, electric vehicles, automotive, home appliances, LED lighting, TVs, power and energy. In the old days an engineering team could build their device with power transistors, then after production run some thermal testing to see if they guessed the proper junction temperature, which in turn effects performance like current drive and Rdon. That approach of build first, measure later leads to product iterations costing time and money. There is a better way today, and it involves simulating the electro-thermal behavior prior to tape-out, while still in the design phase when you have engineering options to improve thermal performance.Related: EDA for Power Management ICs at DAC
One of the challenges for IC designs in general is that as you turn the power supply on then current begins to flow in the transistors, and this current heats up the transistor which then changes the electrical performance of the device. Hot-spots on an IC will decrease the current flow in transistors in that local region. It’s not really accurate to assume that the entire die is at a constant temperature across all dynamic input conditions any more.
Temperature in Top-down, cross-cut view
I followed up with Dundar Dumlugol of Magwelby phone to get more details about their approach to modeling heat flow across chip and package for power devices. They’ve been offering an EDA tool called PTM-ET (Power Transistor Modeler, Electro-Thermal) for the past two years that answers engineering questions like:
- What is the Temperature across my chip?
- How does heat flow as a function of time?
- Where should I place thermal sensors in my IC layout?
- Will my device have thermal runaway?
- What are the IR drops in my layout?
- How does changing my package affect temperature?
How Electro-Thermal Simulation Works
The PTM-ET tool first reads in your IC layout as a GDS II or OpenAccess file, along with a technology file provided by the foundry. Using a 3D solver the simulator can calculate the dynamic currents and Joule self-heating in metal and active area. Active devices are modeled based on SPICE results and internally saved as table models for faster simulation speed. All of the electrical and thermal equations are solved self-consistently by using non-linear, iterative techniques.
With this approach you can model heat conduction through metal interconnect, the substrate, lead frame, clips, bond wires, package and PCB.Related: Ensuring ESD Integrity
With any type of simulation it’s natural to ask how accurate the predicted results are compared with measurements. Results presented at the Therminic 2013 conference show good correlation between simulated and measure results of temperature as a function of time:
These simulated results are within a few percent of measured data, which is accurate enough to make engineering decisions like: changing the IC layout, choosing a different package, making new pad placements, adding contacts, or moving the thermal sensors.
A customer designed a display driver circuit, and the PTM-ET tool then simulated their circuit by creating 250K mesh nodes. To perform 0.5ms of transient simulation required just 10 minutes of CPU time and the simulated results were within 5% of measured values.
Temperature in cross-section Metal and substrate
Another customer design was a power management IC with 23 heat sources, and included the package thermal model. Input for a dynamic Electro-Thermal (ET) simulation came from SPICE and the simulation required under 1 hour of CPU time to cover 2ms of time. A static ET simulation took just 10 minutes of CPU time, using about 1M mesh nodes.
Chip-level ET simulation results
IC engineers designing circuits with power transistors now have a methodology to simulate and analyze the electro-thermal characteristics prior to tape-out. Using such an approach as this will reduce the number of silicon spins required to meet specifications, and confirm that you’ve selected the right package and IC layout to mitigate thermal issues.