Best Practices for IP Reuse

As someone who was heavily involved with rules for IP reuse for many years, I have a major sense of déja vu in writing again on the topic. But we (in SpyGlass) were primarily invested in atomic-level checks in RTL and gate-level designs. There’s a higher level of best practices in process we didn’t attempt to cover. ClioSoft just released a white paper (authored by Jeff Markham) on that topic and forwarded to me by my old Atrenta buddy Simon Rance (now VP Marketing at Cliosoft).

Jeff covers a lot of territory, on creation of IP and evaluation of commercial IP, with his own views on what the industry could do to make these easier. I’m more drawn to the question of what it takes to make an IP reusable because that was a hot topic when we started. There was a book called the IP Reuse Methodology Manual, then considered the bible for what you should and should not do. There’s was also a lot of debate about how practical it was to invest in making internally developed IP reusable.

I heard fairly generally that the effort to make an IP reusable is significant – maybe 3X the original cost of developing the IP. This would be to get it to a point that you could search a library by function, process, parametrics, documentation, that sort of thing, to find and compare this IP with other comparable solutions. Then you could download maybe a behavioral and abstract model to check it out in simulation and a floorplan. Then finally download the full thing with all requisite views and other collateral you would need to use it immediately in your design.

Nice idea and some semi design organizations actually organized to support that development. Perhaps some still do but for many it was a luxury they couldn’t afford. Reuse makes a lot of sense when you have a production line and are pumping out a lot of similar designs, which is what we were all expecting in that era of platform-based design.

Unfortunately for many who believed, markets did a 180 on their original dreams of platform-based design and massive reuse. I’m too disconnected from the details these days to make bold pronouncements, but I wouldn’t be surprised to hear that those dreams went up in smoke. That for most design teams today, reusable IP either comes from IP vendors or reuse has devolved to mean “here’s something fairly close that we used in the last design, adapt it as you see fit for the current design”.

In fact much of the reuse I have seen has evolved further to “we built this chip in the last generation, now it’s going to be a subsystem in this new generation”. Which makes a lot of sense when you think about it. That chip was proven in production, which is a pretty decent (though not perfect) stamp of certification. Good enough anyway when you make payroll by shipping product and you don’t have time to rebuild the subsystem.

Which is not to say that we don’t need to follow reuse best practices, with maybe some selectivity. Good engineering is built on good practices and becomes even more essential as we work on larger designs. Even if you’re going to use “copy and adapt” reuse, you still need to find a best candidate to start from, understand the functionality, parametrics, etc., etc. Maybe there’s something closer to what you need that would be a better starting point. Maybe there’s something in there that will fit the bill exactly – stranger things have happened.

Jeff has a good long list of suggestions. You could save yourselves a lot of time by following them. You can read more about Cliosoft HERE.

Also Read

WEBINAR REPLAY: AWS (Amazon) and ClioSoft Describe Best Cloud Practices

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WEBINAR: Reusing Your IPs & PDKs Successfully With Cadence® Virtuoso®