Getting Low Power Design Right in Mixed Signal Designs

Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog boundaries, let the analog guys do their thing, check (probably manually) very carefully at the interfaces and you should be good, right?

Unfortunately, not so much these days. It’s much more common to find nested analog and digital (some call these sandwiches of analog and digital) for digitally tuning analog performance, using a DSP embedded in an RF section to drive programmable beam-forming, for managing self-test features and other tricks. This greatly complicates defining and checking constraints and verifying through these nested objects.

You no longer have one digital domain touching islands of analog on the periphery. You now have islands of digital floating in seas of analog, floating in seas of digital, … But those digital islands still need to be optimized for power (and for timing, layout and everything else). Manually island-hopping constraints/intent/verification between these digital pieces no longer looks practical.

But whether you are building IoT devices or full-featured mobile platforms, these designs have sensors, they have radios and they have a lot of digital logic, even in the IoT edge nodes. That’s a lot of hungry transistors to feed on a very limited energy budget, so you still have to squeeze every drop of power out of the design. Manual steps have to be automated out, and an automated flow has to start with an infrastructure supporting mixed analog/digital; at Cadence the OpenAccess database is already set up for this.

The infrastructure is in place for passing constraints back and forth between islands through macro-models for the analog pieces. Macro models abstract the analog functionality and enable implementation and verification in the context of the power intent for the design. There is support for timing constraints (of course) and for CPF power intent. In the Virtuoso schematic editor, analog designers can build CPF macro-models which then allow digital designers to stitch these together with the digital components in the context of the power intent. UPF flows also work up to the boundaries of digital circuitry, and since the infrastructure is already in place for CPF macro-model definition and support, Cadence doesn’t anticipate significant development effort to extend this to UPF.

Conformal Low Power can now handle mixed-signal designs as you progress through the design flow. One of the big challenges for everyone in these cases is to minimize false violations. Macro-models and netlisting the design correctly is a central component of this solution; Cadence has created a seamless interface between Virtuoso and Conformal to ease this flow.

Additionally, power-aware dynamic verification before implementation can be challenging due to problems in interpretation and communication of intent at the interfaces between the analog and digital domains. Cadence has done a lot of work in this area to simplify the AMS low power verification flow; this is available for both the CPF and UPF flows.

Power estimation and analysis for mixed-signal designs continues to grow in importance. Analog blocks can be powered down just like digital blocks. Getting to an optimal power solution requires careful and accurate analysis. Cadence’s recently launched Joules product, supporting both both power intent standards, claims to accurately estimate power at the RTL stage and to be within 15% of power seen at signoff.

Handling low power design in modern mixed-signal designs is getting complex. Cadence seems to have most of the tools in place to help. To learn more about the Cadence low power flow for AMS, click HERE.

More articles by Bernard…