Date and time: Friday, December 8, 2023 14:00-15:00
Sponsor: Japan Cadence Design Systems
Innotek Co., Ltd. IC Solution Headquarters
Venue: Online (Zoom webinar)
*You can also participate from a web browser. We recommend using Google Chrome, Firefox, or Chromium Edge.
Registration deadline: December 7th (Thursday)… Read More
Bigger and more complex designs translate to more challenging power, performance, and area (PPA) targets and turnaround time (TAT). The Cadence® integrated digital full flow offers capabilities across individual tool boundaries by integrating core engines and key technologies.
Join us for this DSG CadenceTECHTALK webinar… Read More
When I first saw that Rob Knoth (Product Director at Cadence) had proposed this topic as a subject for a blog, my reaction was “well, how accurate can that be?” I’ve been around the power business for a while, so I should know better. It’s interesting that I jumped straight to that one metric for QoR; I suspect many others will do the same.… Read More
Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog … Read More
When situation demands, multiple solutions appear with a slight lag of time. Similar is the story with estimating and optimizing power at SoC level. In the SoC era, power has become a critical criterion long ago, and there are tools available for power analysis and optimization. However, with more mobile and IoT (Internet of Things)… Read More