FinFETs, Power Integrity and Chip/Package Co-design

FinFETs have brought a lot of good things to design – higher performance, higher density and lower leakage power – promising to extend Moore’s law for a least a while longer. But inevitably with new advances come new challenges, especially around optimizing for power integrity in these designs.

One of these challenges is around power noise. FinFET transistors have high drive strengths; combine that with higher transistor densities and you have higher switching current densities. And because FinFETs enable larger designs, dark silicon (power gating) and voltage scaling become more important across more domains to keep power consumption low. And that leads to higher peak currents (inrush when you turn a domain on, for example). Of course all of this clever power switching and voltage scaling has to be supported by an increasingly complex power distribution system with multiple voltage domains (100+ in some cases) and power gate switches.

These factors drive higher voltage drops in the supply grid, and those voltage drops are more consequential because you are running at lower supply voltages in these technologies. If you compare the power integrity design challenge with a less aggressive technology where you might get 100mV swings on a 1V supply (a 10% swing), now you might face 150mV swings on a 700mV supply (a 21% swing), leaving you with a much lower margin for error. Your dynamic voltage drop (DvD) analysis has to be very complete and very accurate.

This noise issue has become so critical that it is now important to model a per-bump model of the package along with the chip because you really need to co-analyze and co-optimize package and die power and ground networks. That increases the scale of the simulation and analysis task.

Electromigration and self-heating in FinFETs present additional challenges in reliability. Higher drive strengths and thinner wires directly increase EM problems in driven wires, but self-heating raises temperatures around the transistor (since oxide layers isolating the fins limit heat dissipation), and that is thought to potentially affect reliability in neighboring interconnects. (ChipGuy has more on this topic in SemiWiki). So now you need to do not only EM analysis but also thermal-aware EM analysis.

Finally, there’s the usual problem: bigger designs, more complex analysis, so longer run-times. Ansys has analysis solutions in RedHawk for all the problems I have described, but has also made significant advances in distributed multiprocessing (DMP). They already had DMP for simulation, now this has been extended to extraction and data processing and they have been able to demonstrate a 10X speedup on a 1B transistor design. Faster is always good of course, but the impact is more important than that. This level of speedup enables simulating longer time periods which is especially important when checking board integration expectations.

RedHawk has been lead in the power integrity space for over 10 years with 2000+ tapeouts at multiple technology nodes. You can learn more about latest advances in RedHawk analysis by registering for this WEBINAR.

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