ANSYS Talks About Multi Physics for Thermal Analysis at DesignCon

ANSYS makes a big deal of being a multi-physics company. Still it has taken them a while to fully integrate Apache. Nevertheless it seems like there is a compelling argument for combining technologies to solve SOC design problems. Frankly most chip designers would be hard pressed to think of a reason for using computational fluid dynamics (CFD). However it turns out that there is good reason to use it when looking at a comprehensive solution for determining electromigration.

ANSYS’s Ravi Ravikumar shared with me some slides that they are using atDesignCon this week in Santa Clara which outline the flow for thermal analysis of contemporary system designs, such as cell phone processors and other SOCs. Their flow accounts for cases where 3D ICs are used as well. The thing that stands out is that unless you understand the chip in detail along with the environment it is in, including interposer, package, board and cooling regime, you cannot come up with good thermal data – for example like what is needed to determine electromigration effects.

Sources of self heating include dynamic and static device power, as well as on-chip interconnect, bumps and PCB interconnect. Interconnect power consumption goes up linearly with temperature. The real problem is leakage or static power dissipation. We all know at advanced nodes leakage power has grown as a percentage of overall chip power. What is important for electromigration analysis is that leakage power is temperature dependent, dramatically increasing with temperature. So really we cannot talk about how much power the chip is dissipating until we know the temperature. This is where it starts to get interesting.

Until we take first-cut power numbers and propagate them from the chip to the interposer, through the package, board and whatever thermal environment the board is in, we can’t get to the actual power numbers. In fact, once we update the power numbers, we will have new self heating data to propagate again through this flow. It turns out to be an iterative process that eventually will converge. However it requires a tool chain that can accurately calculate results for each level of the design.

In the ANSYS flow here is what this looks like. At the chip level, their Chip Thermal Model (CTM) produced by Totem and/or Redhawk breaks each layer of the chip into small squares and characterizes them at several different temperature points for power consumption. This includes devices and all interconnect layers. With initial temperature information, this can be used by the iterative flow described below to predict power dissipation – leading to better temperature numbers. The chip level information is fed to Sentinel-TI which can take the CTM models to make more compact models that contain thermal information for the die.

Sentinel-TI predicts the thermal behavior of the package. Next we have to consider power dissipation on the board. ANSYS SIwave is used for this purpose. However, unless the housing and external cooling is accounted for these numbers don’t mean anything. This is where ANSYS Icepack comes in with the computational fluid dynamics. You were probably wondering when this was going to get brought up again. Icepack looks at things like airflow and heat transfer in the board housing – i.e. cell phone chassis.

It should be mentioned that different chip thermal models are produced for different modes of operation of the chip. Clearly the power consumed by a chip depends on activity information. Viewing a video will consume much more power than reading email, for instance. The ANSYS flow can accommodate different modes of operation and can even give information about temperature rise given certain usage profiles, such as busts of higher compute intensive usage, etc.

Delving in further there are internal issues in interposer designs that require rigorous analysis. Heat will flow from internal source through the microbumps and/or interposer to get to the exterior of the package. For example, when there are TSVs, there will be metal on the back side of the substrate. This will affect thermal flux. Sentinel-TI can analyze for these and many other cases.

Getting back to the reliability issues related to properly analyzing for electromigration, this flow looks to do a much better job than using guidelines that do not include accurate operating temperature information. Below is a graphic showing calculated electromigration effects with and without consideration of on-chip operating temperature.

ANSYS makes a strong case for using multi-physics for analysis of semiconductor designs. One would be hard pressed to think of another company that can provide a solution that combines such breadth of analysis in solving these tough design problems.

I expect the DesignCon presentation to go into much more detail than I have been able to cover here.