WP_Term Object
(
    [term_id] => 34
    [name] => ANSYS, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 193
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 193
    [category_description] => 
    [cat_name] => ANSYS, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)
            
Ansys IDEAS Digital Forum Banner
WP_Term Object
(
    [term_id] => 34
    [name] => ANSYS, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 193
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 193
    [category_description] => 
    [cat_name] => ANSYS, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)

Efficient Power Analysis and Reduction at RTL Level

Efficient Power Analysis and Reduction at RTL Level
by Pawan Fangaria on 07-22-2013 at 12:30 am

It’s a classic and creative example of design and EDA tool community getting together, exploiting tool capabilities and developing flows which add value to all stake holders including the end consumer. We know power has become extremely important for battery life in smart phones, high performance servers, workstations, notebooks and the like. And these need GPU accelerators, high performance graphic and mobile processors and so on.

Thanks to Nvidia and Apache for making their DAC 2013 presentation (titled – Early RTL Power Analysis and Reduction for Advanced Power-Efficient GPU Designs) available in the form of a free 24/7 available webinar here; for those who couldn’t attend DAC (I am one of them). It was worthwhile to attend this webinar as it increased my knowledge about Apache’s PowerArtist tool and how it could be used by Nvidia in its new, fast and efficient power analysis and power reduction flows at RTL level in its leading edge designs for power and performance intensive graphics.

[Nvidia Power Estimation Methodology]

Miodrag (Miki) Vujkovic from Nvidia talks in great detail about their power estimation methodology and established flows at RTL level by employing PowerArtist to gain on speed (time-to-market) and reduce power with reasonable accuracy.

Miki introduces to RTL PowerArtist Vs Post-Synthesis Primetime-PX based flows and power data analysis with both of them (with experiments performed on tests ranging from 130K to 1.13M instances) which shows leakage power correlation to be within 10% and average dynamic power within 14% (changes with type of tests); total average power correlation being within 4%. He also shows RTL power correlation data with Post-Talus Primetime-PX based flow which is again within reasonable limits. What is interesting is that the RTL PowerArtist flow took about 30X less time (on a single test with single license) compared to Post-Synthesis flow; quite efficient! Miki also explained methodologies for improving power estimation for different cell categories like RAM and FFs.

[Hierarchical Power Reporting GUI]

PowerArtist has quick and easy setup procedure and it provides excellent GUI for hierarchical power exploration, design traversal, cross-probing etc. It also provides useful commands such as calculatePower, reportPower for reporting power consumption at each hierarchy level. The tool enables designers to use OADB APIs and TCL API layer to investigate various power related information in the design and even develop powerful scripts to create customized reports. Some of the useful commands of frequent use are getCGs, getCGRegisters, getCGInfo, reportCGEfficiency and so on.

[PowerArtist RTL and Clock Power Reduction]

Talking about power reduction flow, PowerArtist provides clock enable generation and strengthening for both sequential and combinational logics, gating memory clocks, memory splitting, redundant memory cycle elimination, redundant computation identification and datapath operand isolation. Special sequential and combinational techniques are used for clock power reduction. Power wastage is identified and quantified.

[PowerArtist LER technique to reduce power]

LER (Low-activity Enabled Register) technique identifies major areas of possible power reductions as is evident from Nvidia’s testcases.

[PowerArtist Gate Memory Clocks to reduce power]

PowerArtist identifies redundant memory cycles and wasted power and gives precise user guidance for changing RTL source.

[Cumulative Average Power Savings in Nvidia Designs]

It’s implied to prioritize power reduction opportunities with max number of hits and max average power saved across all tests. A study of cumulative average power saving shows that 3 to 4 small code changes may fix 20 or more top suggestions.

Overall, it’s a nice proposition for early power analysis and reduction at RTL stage to significantly speed up the overall flow, yet achieve estimated power within 20% of sign-off power. Beauty of the tool is that it exactly points to source file and line number for code changes in order to save power. And one can sort suggestions with largest impacts first. I would highly recommend going through this webinarto know more and consult Nvidia and Apache for more details, if needed. The webinar is available online until 15 Oct 2013, 10 AM PDT.


Comments

There are no comments yet.

You must register or log in to view/post comments.