Last week I talked to Eileen You of Samsung-SSI to get a preview on what they will be talking about at Apache’s customer theater at DAC. Their presentation is titledThe Life of PI: SoC Power Integrity from Early Estimation to Design Sign-off. The ‘PI’ stands for Power Integrity.
Samsung-SSI’s operations are 5 years old and have grown from 1 person to 100 and have gone through several generations of technology. Some designs are 28nm and other are currently below.
Apache tools are used to generate scenarios for power analysis and integrity. Power analysis is dependent on vectors for realistic scenarios but that is a really hard challenge they find. They are trying to expand up to the RTL level since there is too little gain from doing analysis post-synthesis since the design is hard to change.
Primarily Samsung are using RedHawk, CPM and Sentinel. Redhawk for general power analysis. For package and board they use Sentinel. Packages need to be analyzed in the frequency domain and in the time domain.
The future challenges they see are mostly big picture stuff: power grid design, power regulators, keeping costs under control with the right metal stack, and, of course, the big one that everyone faces that power density is increasing. Rocket nozzles anyone? As designs get bigger and processes have less margin, obviously higher accuracy, higher capacity. Plus getting good power vectors so that the analysis done is realistic. It is easy to waste a lot of time doing very accurate analysis with bad vectors.
The abstract of Samsung-SSI’s presentation: The life of Power Integrity (PI) analysis starts at the product infancy stage. Early analysis involves resource allocation at the system level, such as the VRM, board, and package, and at the chip level, in terms of power grid structure, power scenario analysis, and the amount and placement of intentional decoupling capacitance (DECAP). This is done through systematic PI modeling and simulation. As the design matures, the power integrity engineer gets more information on the system and on the die. There are many phases of progressive iterations to evaluate design tradeoffs. Power integrity engineers work closely with board, package, and chip design teams to achieve PI closure. At the design tape out stage, the power integrity team is responsible for signing off static and dynamic IR drop and EM to verify that multi-million gates SoC chips meet stringent power supply noise budget. We investigated the impact of board, package, package embedded with DECAP, power grid, circuit switching activity, as well as on-die DECAP and demonstrated good correlation between early estimation and the final analysis with detailed chip and package models.
To register for this or other customer presentations at the Apache booth at DAC go here.
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